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In this paper, we propose a novel approach to voltage island formation and core placement for energy optimization in manycore architectures under parameter variations at pre-fabrication stage. We group the cores into irregular "cloud-shaped" voltage islands. The islands are created by balancing the desire to limit the spatial extent of each island, to reduce PVT impact, with the communication...
In the future multi-processor system-on-chip (MPSoC) platforms are becoming more vulnerable to transient and intermittent faults due to physical level problems of VLSI technologies. This sets new requirements to the fault-tolerance of the messaging layer software which applications use for communication, because the faults make the operation of the Network-on-Chip (NoC) hardware of the MPSoCs less...
A circuit block model and methodology for accurate power supply noise analysis, taking the impact of power supply noise on the current consumption into account, is presented. This enables high transient accuracy even at excessive power supply noise. Further improvement is obtained by an adaptive model for the capacitance of switching gates. Simulations for various power grids and test circuits are...
Mapping an application on multiprocessor system-on-chip (MPSoC) is a crucial step in architecture exploration. The problem is to minimize optimization effort and application execution time. Simulated annealing (SA) is a versatile algorithm for hard optimization problems, such as task distribution on MPSoCs. We propose an improved automatic parameter selection method for SA to save optimization effort...
This paper presents energy and bandwidth aware topological mapping of intellectual properties (IPs) onto regular tile-based network-on-chip (NoC) architectures. One-one mapping as well as many-many mapping are being taken in to consideration between switches and tiles in the proposed approach. In view of minimizing energy and link bandwidth requirements of the NoC-based designs, the approach focuses...
High level design-space exploration methodologies focus on optimizations on application and architectural abstraction layer. For power, leakage, and cost sensitive, as well as for performance critical SoC building blocks like embedded domain-specific processors and application specific accelerators, parasitic physical realization effects strongly influence the actual architecture efficiency. The tradeoff...
This paper presents an intrinsically verifiable library of quasi delay insensitive asynchronous templates providing an efficient debugging platform for large asynchronous circuits. We proposed using state transition graph to determining necessary properties which must be checked. For every template of a pre-charged full buffer library, we defined PSL properties which are used as monitors verifying...
In this paper an analytical study on dynamism and possibilities on slack exploitation by dynamic power management is presented. We introduce a specific workload decomposition method for work required for (streaming) application processing data tokens (e.g. video frames) with work behaviour patterns as a mix of periodic and aperiodic patterns. It offers efficient and computationally light method for...
Network-on-chip (NoC) has been used as the new on-chip communication paradigm. Asynchronous NoCs are power efficient and robust to process variation but they are slow. One reason for the low speed is the way that asynchronous routers use to build wide channels. To meet the bandwidth requirement, current routers broaden their channels by synchronizing multiple sub-channels. The C-element and buffer...
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