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A novel architecture of the configurable Distributed Random Access Memory (RAM) logic based on Look-Up Tables (LUTs) in the Logic Block (LB) is proposed and implemented in a tile-based FPGA manufactured with a 0.5μm SOI-CMOS logic process. The Distributed RAM can be configured in two modes: Single-Port RAM and Dual-Port RAM. Due to its resource abundance and low latency the Distributed RAM can complement...
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