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Fault tolerance is an important system metric to increase chip reliability. The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume and weight. In this contribution, we propose a technique based on partial dynamic reconfiguration (PDR) to tolerate faults in configurable...
Reduced Precision Redundancy (RPR) is demonstrated as a new method for improving fault tolerance in Field Programmable Gate Arrays (FPGAs) replacing Triple Modular Redundancy (TMR) to protect against the Single Event Effects due to radiation in arithmetic processes. As a test of this approach, the RPR technique was used to implement a Radix-4 Fast Fourier Transform (FFT). This design was implemented...
In recent years, many techniques for self repairing of the systems implemented in FPGA were developed and presented. The basic problem of these approaches is bigger overhead of unit for controlling of the partial reconfiguration process. Moreover, these solutions generally are not implemented as fault tolerant system. In this paper, a small and flexible generic partial dynamic reconfiguration controller...
This paper proposes the design of a controller managing the fault tolerance of multi-FPGA platforms, contributing to the creation of a reliable system featuring high flexibility and resource availability. A fault management strategy that exploits the devices' reconfiguration capabilities is proposed, the Reconfiguration Controller, focus of this paper, is the main component in charge of implementing...
Asynchronous circuits possibly have several potential advantages in comparison with synchronous one. In this paper, we attempt to introduce asynchronous circuit design method into the control unit of our 8-bit microprocessor by the burst-mode design method and implemented the asynchronous 8-bit microprocessor with outputs to observe all registers and the program counter by using a standard FPGA development...
A method how to improve the coverage of single faults in combinational circuits is proposed. The method is based on Concurrent Error Detection, but uses a fault simulation to find Critical points - the places, where faults are difficult to detect. The partial duplication of the design with regard to these critical points is able to increase the faults coverage with a low area overhead cost. Due to...
According to the shrinking feature size of the VLSI circuits it is expected that nano scale devices and interconnections will introduce unprecedented level of defects and architectural designs need to settle with the uncertainty result at such scales. Several approaches for implementing the fault tolerance systems are already investigated. Most of these methods are applicable also in the case of high...
Side channel attacks and more specifically fault, simple power attacks, constitute a pragmatic, potent mean of braking a cryptographic algorithm like RSA. For this reason, many researchers have proposed modifications on the arithmetic operation functions required for RSA in order to thwart those attacks. However, these modifications are applied on theoretic - algorithmic level and do not necessary...
We present a fault-tolerant post-mapping resynthesis for FPGA-based designs that exploits the dual-output feature of modern FPGA architectures to improve the reliability of a mapped circuit against faults. Emerging FPGA architectures, such as 6-LUTs in Xilinx Virtex-5 and 8-input ALMs in Altera Stratix-III, have a secondary LUT output that allows access to non-occupied SRAM bits. We show that this...
While stability and robustness of synchronous circuits becomes increasingly problematic due to shrinking feature sizes, delay-insensitive asynchronous circuits are supposed to provide inherent protection against various fault types. However, results on experimental evaluation and analysis of these fault tolerance properties are scarce, mainly due to the lack of suitable prototyping platforms. Using...
Fault-tolerant architectures based on physical replication of components are vulnerable to faults that cause the same effect in all replica. Short outages in a power supply shared by all replica are a prominent example for such common cause faults. For systems in which the provision of a replicated power supply would cause prohibitive efforts the identification of reliable countermeasures against...
Field programmable gate arrays offer flexibility to program hardware systems together with the possibility to explore any level of parallelism available in the application. Unfortunately, this flexibility costs a huge amount of circuit area necessary to implement all the routing switches and wires. Also, device scaling in new and future technologies brings along a severe increase in the soft error...
The problem of planning the overlaps of multiple alternative configurations is critical to maximize the reliability of a reconfigurable fault-tolerant system based on field programmable gate arrays. To address the problem, an unnecessary assumption made in previous work is removed and a second-order approximation domain-partition method is proposed. Experimental results on ITC99 benchmark circuits...
The ongoing miniaturization of digital circuits makes them more and more susceptible to faults which also complicates the design of fault tolerant systems. In this context fault injection plays an important role in the process of fault tolerance validation. As a result many fault injection tools have emerged during the last decade. However these tools only operate on specific domains and can therefore...
This work presents a method that allows dynamic partial reconfiguration with triple modular redundancy in SRAM-based FPGAs fault-tolerant designs. Experimental results show reduced time and energy in fault recovery compared to XTMR with scrubbing.
Designing dependable systems is a systematic task where area, power and performance are competing constraints. In many applications, design restrictions do not permit the total hardening of a design, leaving some internal circuitry vulnerable to radiation effects. Hierarchical analysis is necessary to identify the relative importance and vulnerability of individual sub-circuits in a design so that...
We propose a hybrid FPGA architecture with a dense and defective nano-crossbar serving as its configuration memory. An amorphous routing architecture is adopted to optimally allocate logic and routing resource on per-mapping basis and to achieve high logic density. This hybrid FPGA is designed to be efficient in using nano-crosspoints, highly tolerant to memory defects, and versatile to provide features...
The following topics are dealt with: process variations aware design; physical design; ATPG and fault tolerance; SOC and NOC design; digital design methods; ASIC and FPGA design; design verifications; analog test; BIST and MEMS test; and SOC and memory tests.
Mission-critical applications such as space or avionics increasingly demand high fault tolerance capabilities of their electronic systems. Among the fault tolerance characteristics, the performance and costs of an electronic system remain the leader factors in the space and avionics market. In particular, when considering SRAM-based FPGAs, specific hardening techniques generally based on Triple Modular...
The following topics are dealt with: memory test, online testing & test generation; mixed signal and RF design; FPGA-based design; BIST; fault tolerance and analysis; DFT and low power design; fault modeling & analysis; design verification & optimization; analog and mixed-signa test; SOC/NOC/MPSOC; and layout design & verification.
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