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We describe our experience introducing DSP concepts via an FPGA-based advanced digital design course. The students had previously taken an introductory digital design course and a continuous-time linear systems course; a few were taking an introductory DSP course concurrently. Through a series of weekly lab exercises, the students learned advanced FPGA design methods while progressively constructing...
FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. As in many multithreaded applications, communication and synchronization incur significant overheads. Even if these challenges are overcome, the large graph data structures used can quickly...
Fixed-point simulation is extremely important in the design of fixed-point FPGAs. Float-point simulation is used to verify the arithmetic, while the fixed-point simulation is adopted to evaluate performance and verify the implementation. The design of high-precision system by FPGAs must focus on the fixed-point simulation to reduce the error acceptable even to zero. Based on the analysis of fixed-point...
To enable 40Gb/s data transmission over optical fibres using QPSK modulation, the first step of the receiver signal-processing pipeline is a 128-tap FIR filter that compensates the chromatic dispersion due to the medium. We present an implementation of this FIR filter in the largest Stratix-IV GX device that is able to process 20 giga-samples per second, where each sample is a complex number with...
A general-purpose multi-channel radar echo simulator is researched and proposed in this paper to satisfy the various needs of the radar signal processor testing. The specificity of target echo model is the main problem to achieve the generalization for a simulator. The simulator will give priority to the issue of the generalization because the generalization is always the most attractive feature for...
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGA-based systems. The clock-gating techniques are used to reduce the total power of the system. To achieve this, we reduce clock power consumption of the system by switching-off the clock signal for the parts of system that are not used. The system presented in this paper is based on the main...
This work presents the hardware and software architecture for the detection of fractures and edges in materials. While the detection method is based on the novel concept of Low Transient Pulse (LTP), the overall system implementation utilizes two microelectronics technologies: Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). The DSP carries out the analysis of the received...
Synchronous dataflow (SDF) is an ubiquitous dataflow model of computation that has been studied extensively for efficient simulation and software synthesis of DSP applications. In recent years, parameterized SDF (PSDF) has evolved as a useful framework for modeling SDF graphs in which arbitrary parameters can be changed dynamically. However, the potential to enable efficient hardware synthesis has...
Aim of this paper is to compare and prove implementation of normal multiplication and Vedic multiplication (using Urdhva Tiryakbhyam Sutra) on digital hardware requires same number of multiplication and addition operations.It makes difference only for mental calculations. Few VHDL codes has been developed for this. All multipliers has been tested for 16 ?? 16 multiplications for comparison. Test vectors...
This paper gives the circuit design for logistic digital chaotic system, with the analysis of parameter selection for logistic cipher code, effecting factors and calculating method of sequence cycle. Through experiments it is shown that different calculating precisions and u value can be the factor that effects the cycle period most, changing u value can change the cycle and the larger precision can...
This paper presents a comparative study of field programmable gate array (FPGA) implementation of standard and truncated multipliers using very high speed integrated circuit hardware description language (VHDL). Truncated multiplier is a good candidate for digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transform (DCT) etc. Significant reduction...
Fast Fourier transform (FFT) is an essential component in many digital signal processing and communications systems. The performance of the FFT component is a key factor in evaluating the overall system performance, and it is common to use it as a benchmark for the whole system. Many attempts have been made to enhance the FFT performance, both on algorithm and implementation levels. Software and hardware...
In this paper, according to the basic theory of digital modulator, the design model of digital modulator is built by using the improved Direct Digital Synthesizer (DDS) technology through running the Matlab/DSP Builder environment. Firstly,analyse the function of each module in this model and simulate the grade of algorithms to it and also produce VHDL language, then carry on Register Transport Level...
FPGA development tools can be complex, especially for users outside the digital design space. As a result of this complexity, industry is calling for software tools to increase efficiency of digital designers by abstracting the low-level details of FPGA programming. Most importantly, this process must close the growing gap between hardware and software design. New tools are emerging to help scientists...
In the industrial production area, pressure is one of the important measuring parameters. To ensure the measurement accuracy of pressure sensors, it is necessary to carry out a regular calibration on them. In order to obtain the standard value of pressure accurately, rapidly and continuously, a high-precision hydraulic calibration system based on DSP and FPGA was designed. The pressure signal of hydraulic...
Custom operators, working at custom precisions, are a key ingredient to fully exploit the FPGA flexibility advantage for high-performance computing. Unfortunately, such operators are costly to design, and application designers tend to rely on less efficient off-the-shelf operators. To address this issue, an open-source architecture generator framework is introduced. Its salient features are an easy...
When implementing a mathematical function in h/w, we would like to minimize the required resources. This task is critical in FPGA designs. One of the popular techniques for implementing mathematical functions in h/w, is a lookup table (LUT) based design. In order to reduce the required memory size, the common implementations use a pre-defined set of input values for which the function values are stored...
Todaypsilas systems are more complex and need higher performance. To accomplish this, systems include more hardware compared to software. This increases the use of FPGAs in modern systems because of its reconfiguration capabilities. FPGA contains many hardware components, which are utilized to perform operations directly in hardware. There are two problems related to this issue, first is high performance...
This paper proposes a digital control system with features of high productivity and reconfiguration, which is named HPRDCS. The system is partitioned into two subsystems with three layers and implemented based on a single FPGA chip. The control subsystem performs basic control functions using hardware methods based on HDL languages, thus forms the hardware real-time layer. The embedded subsystem with...
This paper studies on the hardware design and implementation of a universal multi-DSP and FPGA image information processor in accordance with the PCI-E and CPCI specifications. The image information processor features two clusters of total four ADSP-TS201 TigerSHARC DSPs from ADI as the kernel processing unit, reconfigurable framework implemented by two Xilinx Virtex-5 FXT FPGA chips. Taking full...
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