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Thermal resistance data were collected using two different style flip chip ball grid array (FCBGA) packages; one with an exposed molded die and a second with a lid. Eleven different heat sink designs and two different thermal interface materials (TIM) were tested to quantify the thermal interaction between heat sink size, base material and TIM resistance as a function of package style. Package style...
A two-die stacked silicon module with TSV has been developed in this work. Thermal-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process....
A demand for small form factor in IC packaging has lead to a reduced bump size and an increased current density. The high current density accompanying with Joule heat induces an electromigration failure. In this study, we investigated the effects of under bump metallization (UBM) on the electromigration failure. Three types of UBM such as Cu 5 μm, Cu 10 μm and Cu 5 μm/Ni 2μm were compared with 60...
In this paper, the investigation focuses on the copper stud bump solder joint thermal-mechanical reliability. The copper stud bump processing is simulated by FEM software Ansys/Ls-dyna, and then the relationship between the copper stud bump and processing parameters (bonding force, ultrasonic power, bonding time and bonding temperature) is studied. Based on the simulation result, the dimension of...
Recently the requirement for portable products, such as mobile phones, digital cameras, PDAs and game consoles, has been increasing rapidly and consumers want to easy to carry them and have multi-functions as well as lower price. So it's necessary to develop the semiconductor packages with thin and small size, high performance and low cost. And various types of SiP (system in package) technologies...
Elelctrochemical migration (ECM) test was conducted for fine pitch flip-chip micro bump interconnect. Two kinds of micro bump. i. e., Cu post with SnAg solder and Cu under bump metallization (UBM) with SnAg solder bumps in 50 and 100 ??m pitch with non clean flux were used for chip interconnection. The test was conducted under 85??C/85H condition with various biases. The results indicated that for...
In the case of field programmable gate array (FPGA) chips, as the demand for higher speeds and enhanced functionality increases, the size of the flip chip die grows accordingly to offer higher number of logic cells. Large flip chip die also requires a large package for efficient signal routing. This paper shows a warpage improvement study including lid design and process optimization to solve warpage...
Further miniaturization of electronic systems is approaching new limits due to the failure mechanism of electromigration. Electromigration results in a transport of material in solder joints subjected to high electrical current densities. This decreases the system reliability and, therefore, it is necessary to assess and quantify this failure mechanism in solder joints. In this paper we discuss the...
Three parameters, copper pad material, pad thickness, and bump patterns were chosen as three control factors. By using an L9(34)orthogonal array the copper stud bump solder joints which have 9 different combinations of parameters were designed. The finite element analysis models of 9 copper stud bump solder joints were established by using ANSYS/LS-DYNA, and analyzed the finite element tensile simulation...
Electromigration (EM) of micro bumps of 50 mum pitch was studied using four-point Kelvin structure. Two kinds of bumps, i. e., SnAg solder bump and Cu post with SnAg solder were tested. These bumps with thick Cu under bump metallization (UBM) were bonded with electroless Ni/Au (ENIG) pads. The results showed different EM features comparing with larger flip chip joints. Under various test temperatures...
Flip chip packaging of ultra fine pitch integrated circuits (ICs) on organic substrates aggravates the stress-strain concerns, requiring a fundamentally different system approach to interconnections, underfill, interfaces, and the substrate. This work demonstrates a novel interconnection solution with excellent reliability for ultra-fine pitch (~30 mum) silicon (Si) on organic first level interconnections...
Flip chip solder joints made with Cu and Ni underbump metallurgy (UBM) on the chip under current stressing were studied. The effects of material and various thicknesses (5, 10, 15, and 20 mum) of UBM on reliability were investigated. The solder material used was lead-free (Sn4.0Ag0.5Cu). Time to failure of both cases (Cu and Ni UBMs) was forecasted through the physical damage occurring at the bump...
The electromigration of flip chip solder joints is an ongoing reliability concern for manufacturers of integrated circuit (IC) components and electronic systems. As power levels of ICs continue to increase, current densities within individual solder bumps often increase, along with the operation temperatures of the die surface. Both of these factors have detrimental impact on the electromigration...
In this paper we present the results of a study done to compare and contrast BCB and ALX polymers in typical WLP structures fabricated at RTI. Based on initial studies of the materials vendor, Asahi Glass Corp, AGC, we have examined the processing parameter space of ALX-211, in order to develop scalable manufacturing processes for these films. We present process flow and photo property data on ALX-211,...
The introduction of lead-free bumps into flip chip packages in combination with the incorporation of Cu / low-k or ultra low-k dielectric materials is making underfill development more challenging. The traditional concept of stiff and rigid underfills does not satisfy the new device reliability requirements. Rather, newer generation underfill materials need to balance the physical properties, such...
This paper discloses an ultra-thin and highly flexible package with embedded active chips. In this structure, there are no any supporting and permanent substrates needed. A 3 um copper foil with 18 um carrier layer was used as temporal substrate. The carrier layer will be removed after chip embedded process. After patterning and etching processes, the temporal copper foil became the bottom circuit...
This work describes the development and evaluation of advanced technologies for the integration of electronic die within membrane polymers. Specifically, investigators thinned silicon die, electrically connecting them with circuits on flexible liquid crystal polymer (LCP), using gold thermo-compression flip chip bonding, and embedding them within the material. Daisy chain LCP assemblies were thermal...
Thermo-mechanical modeling has been done in a true-symmetry three-dimensional geometry for copper-pillar flip-chip packages to find out package warpage, stress and bump joint strain energy during temperature cycling. Lead-free solder materials, SnAg and SnAgCu were used in the bump joint at the substrate side. The strain energy due to both time-independent plastic and creep had been considered during...
The impact of Chip-Package Interaction (CPI) which is caused by the mismatch in the coefficient of thermal expansion (CTE) between substrate and chip in a Flip Chip Ball Grid Array (FCBGA) on the mechanical reliability of Cu/Ultra low-k in a larger die was investigated using Finite Element Analysis (FEA). In order to associate the deformation and thermal stresses in FCBGA with those in the Cu/Ultra...
This paper focused on design, assembly and reliability assessments of 21 ?? 21 mm2 Cu/Low-K Flip Chip (65 nm technology) with 150 ??m bump pitch. Metal redistribution layer (RDL) and polymer encapsulated dicing lane (PEDL) were applied to the chip wafer to reduce the shear stress on the Cu/low-K layers and also the strain on the solder bumps. The first level interconnects evaluated were Pb-free (97...
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