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The group IV elements doped ZnO thin-film transistors (TFTs) were deposited by radio-frequency magnetron sputtering on substrates at 150 . The influence of the dopant concentrations on the device performance was examined. Device characteristics such as threshold voltage were modulated and field effect mobility and saturated current could...
We have evaluated multiple-input NAND circuits using polycrystalline silicon thin-film transistors and found that the output pulse became degraded for the 3-input NAND circuit. Moreover, we have fabricated a set-reset flip-flop (SR-FF) circuit using the 2-input NAND circuits and confirmed that the SR-FF circuit operated correctly.
As an inevitable effect of scaling, various short-channel effects have become serious matter of concern for semiconductor industry. The scenario gets more complicated as the channel length shrinks to deca-nanometer range and quantum mechanical effect comes into picture. In this paper, a quantum analytical threshold voltage roll-off and DIBL model for Dual Material Double Gate (DMDG) MOSFET is presented...
Junctionless Nanowire Transistor (JLNWT) is now being considered one of the most attractive and deserving candidate for future ULSI applications due to its high current driving capability and better SCEs immunity. In this paper, a semi-analytical subthreshold current model has been developed for short channel JLNWT including interface trap charges (ITC) density. This paper explores the electrical...
This Paper elucidate the development of SOI-MOSFET using different gates like single, double, triple and gate all around structures. It is the Si MOSFET that is a fundamental device in the development of very high density Integrated Circuits. Thus SOI Technology is used for reducing the Parasitic Capacitances. Improvement in the electrostatic control by gate of the channel is done with the increase...
Short channel effects in double gate poly-Si SLS ELA TFTs are studied in this work by electrically characterizing devices with varying top gate length and constant bottom gate length. The electrical parameters were extracted for different bottom gate biases, observing a Vth increase with increasing channel length, attributed to more traps present within larger channels. This was also probed through...
We fabricated highly reliable a-InGaZnO thin film transistors (TFTs) with new silicon nitride (SiNX) gate insulator (GI) fabricated at low temperature (150°C). This new SiNX layer has low hydrogen content which is controlled by the source gases. Hydrogen gas flow rate ratio to SiF4 was changed as 0%, 1%, and 8%, but the bias-stress-induced threshold voltage instabilities on the three kinds of TFTs...
The PECVD silicon oxy-nitride film has been widely used as antireflective coating (ARC) and contact etch stop layer (CESL) in IC fabrication. It is typically deposited using SiH4&N2O gas mixtures at temperatures around 400°C, with film properties such as reflective index, wet etch rate, stress and uniformity controlled by varying gas flows, RF powers, temperature and pressures. In addition, the...
A brief presentation of the NOI — Nothing On Insulator — nanotransistor, followed by two theoretical points of view concerning the NOI-FET non-linearity are presented in this paper. The main target is to prove the NOI nanotransistor affiliation to the FETs family, monitoring the gate-control on the drain current. The drain current is activated by the VDS voltage under tunneling conditions. The gate...
In this paper, we analyze, for the first time to our best knowledge, the high-temperature perspectives of Ultra-thin body (UTB) SOI MOSFETs. High-temperature behavior of threshold voltage, subthreshold slope, transconductance maximum and on-current is analyzed in details through measurements and 2D simulations. Particular attention is paid to the effect of buried oxide (BOX) and Si film thicknesses...
The performances of thin-film-transistors (TFTs) with the channel region crystallized by metal-induced-lateral-crystallization (MILC) before and after patterning are compared. TFTs are experimentally fabricated to study current drive, off-state leakage current, subthreshold slope, threshold voltage, and drain induced barrier lower (DIBL). The superiorities of TFTs with channel crystallized after patterning...
We demonstrate that Fully Depleted Silicon-On-Insulator (FDSOI) technology is a simple and mature alternative to the bulk one for the 22nm technology node and beyond. In particular, this technology allows significant improvement of the transistors electrostatic control and variability. Furthermore, the integration of such FDSOI transistors on an ultra-thin buried oxide allows their scalability down...
Organic memory devices were realized using oxadiazole-containing polyether as active organic layer. A thin film containing this molecule was sandwiched between n-type silicon substrate (cathode) and aluminum (anode) electrodes. The memory cells showed an on-off ratio of 4.9 orders of magnitude at 1.3 V and a threshold voltage of about 2.9 V. The analysis of transport was realized considering space...
Negative charges were tunneled from Si surface into nitride film in the nitride/oxide/Si stacks by bias or corona charging. The tunneled charges appear to have linear relationship with the applied electrical field. A maximum negative charge density exists, when all K centers in nitride film are negative charged. At high bias condition, Si interface will take the risk of high energy electron damage...
We have developed analytically a threshold voltage model and explored the threshold voltage roll-off and drain-induced barrier lowering (DIBL) effects for undoped surrounding-gate (SG) MOSFETs. The model is derived by applying the Gauss law by considering an elemental area of the channel rather than using Poisson equation as implemented earlier. For this threshold voltage model, the threshold voltage...
Two dimensional numerical simulation of nanoscaled selective buried oxide (SELBOX) based MOSFET is performed. In this device an opening is provided under the device channel in the buried oxide (BOX). A comparative analysis of the SELBOX, bulk and SOI (Silicon-on-Insulator) devices for various performance measuring parameters has been done. The simulation study has revealed that by properly choosing...
The successful fabrication of hybrid SOI-GeOI wafers is reported. Process alternatives are documented by detailed characterizations. This co-integration achieves high hole mobility in Ge islands and high electron mobility in Si islands.
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
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