The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Assembly process reliability for Optical Multi-Chip Modules (MCM) is studied and improved. In the optoelectronic (OE) chip assembly for the Optical MCM, the OE chip with Au stud bump is joined with Sn-Ag-Cu (SAC) soldered in a through-waveguide via on an organic substrate to obtain high optical coupling efficiency. Since solid-liquid diffusion of Au to molten SAC is rapid, and formation of brittle...
In this paper, we investigated the reliability test for Glass interposer. The test vehicle is assembled glass interposer with chip, BT substrate, and PCB. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass...
Silicon interposer has emerged as a substrate of choice for integrating fine pitch, high density devices. Conventional packaging of 2.5D/3D devices involves multiple level of assemblies. Normally, 2.5D/3D devices are first assembled on thinned silicon interposer with aspect ratio of 10:100 followed by second level assembly on a multi-layer organic build-up substrate. In this study we introduce direct...
Moisture voiding in underfill materials can cause reliability issues for the flip chip packages. The bake-out step included in the assembly process flow to avoid this problem cannot be completely efficient for some large die size packages. This is due to complex substrate circuit designs and time delays subsequent to the bake-out step. This paper proposes using the variable frequency microwave cure...
Bond-Via-Array (BVA™) technology has been developed to address the high density interconnect requirements of the next generation of package-on-package (PoP) solutions. This technology, while utilizing conventional assembly processes and equipment, can provide more than 1000 interconnections between the memory and the logic packages when stacked in a PoP format within a standard PoP package footprint...
A 3D system-in-package (SiP) module for pakage-on-package (PoP) application base on the commercial multi-layer printed circuit board (PCB) using BT laminated substrate is presented in this paper. To achieve the miniaturized package-level 3D SiP, double-sided SMT process and a stacked interposer as the interconnection of IO signals were selected. One ASIC and three ADC were mounted on the top of the...
This paper mainly does research about the multilayer chip embedded based on the organic substrates. On the one hand, that puts forward a new 3D package structure of the organic substrates embedded. On the other hand, we find a kind of process flow based the whole organic substrate process and solve the key process. We completed the sample and test of the single-layer chip based the multilayer chip...
Low melting 57Bi42Sn1Ag (BiSnAg) was explored for replacing SAC solders as a low-cost solution. In this study, BGAs with SAC105, SAC305, and BiSnAg balls were assembled with SAC105, SAC305 or 57Bi42Sn1Ag solder paste. Joint mechanical strength, drop test performance, and voiding performance were evaluated against the reflow profile. SnPb was included as a control. The findings are as follows: (1)...
This paper summarizes key learnings on 20/16nm CPI (Chip-Package-Interaction) challenges at 100um pitch and below to support ever increasing performance/cost/form factor demands for high performance mobile SoCs. CPI solutions for two types of Cu pillar interconnects using mass reflow and thermal compression type assembly process respectively are studied in technology development/production, and separate...
The icPhotonics™ optical module assembly development was presented in [1]. The module allows for aggregate full duplex data rate of better than 1.30 Tb/s with Bit Error Rate (BER) < 1E-12 into and out of a single ASIC die for distances up to 300m. The module assembly uses standard semiconductor processing equipment and materials. The icPhotonics™ components — an organic interposer (substrate),...
During last couple years, the market of IC package have successful to implement Cu Pillar Flip Chip Technology as a mainstream of high density flip chip solution in each of portable markets(mobile phone, tablet & lots of portable entertainment solution). Moreover, concerning about high end product application which required 10∗10mm above die area on larger flip chip ball grid array product, the...
This paper mainly does research about the multilayer chip embedded based on the organic substrates. On the one hand, that puts forward a new 3D package structure of the organic substrates embedded. On the other hand, we find a kind of process flow based the whole organic substrate process and solve the key process. We completed the sample and test of the single-layer chip based the multilayer chip...
A 3D system-in-package (SiP) module for pakage-on-package (PoP) application base on the commercial multi-layer printed circuit board (PCB) using BT laminated substrate is presented in this paper. To achieve the miniaturized package-level 3D SiP, double-sided SMT process and a stacked interposer as the interconnection of IO signals were selected. One ASIC and three ADC were mounted on the top of the...
Low melting 57Bi42Sn1Ag (BiSnAg) was explored for replacing SAC solders as a low-cost solution. In this study, BGAs with SAC105, SAC305, and BiSnAg balls were assembled with SAC105, SAC305 or 57Bi42Sn1Ag solder paste. Joint mechanical strength, drop test performance, and voiding performance were evaluated against the reflow profile. SnPb was included as a control. The findings are as follows: (1)...
Each new technology node brings new design and technology challenges making it harder to maintain Moore's law in a cost effective way. Maintaining cost effectiveness is becoming a major challenge for IDMs, fabless companies and foundries. 3D/2.5D technologies offer some unique advantages over traditional scaling such as higher power efficiency, higher bandwidth and heterogeneous integration which...
The adoption of Tablet devices within the mobile communication space and its penetration into the market segment once held by laptops has resulted in explosive growth rate of these devices, and as a result has created new requirements for the packaging of Application Processors (AP) used in these devices. These requirements and trends are similar to those seen within the Smartphone space and include...
In order to achieve high speed transmission and large volume data processing, large size silicon-interposer has been required. Warpage caused by the CTE mismatch between a large silicon-interposer and an organic substrate is the most significant problem. In this study, we investigated several warpage control techniques for 2.5D package assembly process. First was assembly process sequence. One is...
This paper presents results for assembly and reliability evaluations performed while developing a first of its kind heterogeneous 2.5D HiCTE Ceramic Field Programmable Gate Array (FPGA) package. The heterogeneous device discussed here is a three dimensionally stacked FPGA device integrated with a 28G Transceiver die using a passive interposer. Several thousands of micro bumps are used for making connections...
With increasing data traffic requirements to support mobile devices, tablets and computers, the need for faster internet traffic is mushrooming. The routers and switches used to drive network traffic need to deliver high bandwidth and speed. Key to achieving this high speed and bandwidth is ensuring closer integration between the Application Specific Processors (ASICs) and Memory devices. Consequently,...
Just in few years, three-dimensional (3D) packaging technologies have attracted much more attention. With emergence of through-silicon via (TSV) technology, silicon-based device integrations, the TSV's, have become the main stream of 3D packaging technologies. TSV's can be further classified as 2.5D and 3D TSV's. For 2.5D TSV package assembly, since multiple components involved, there are normally...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.