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Charge sensitive pre-amplifier architectures have been studied for decades for various applications, most of which adopt a gain stage with capacitor feedback to integrate the signal and a reset path to provide DC bias. For the biological temperature readout front-end, we propose a novel structure without the gain stage, which implies a strong potential for fully integrated high frequency applications...
In this paper, we present a compact and low power bandpass amplifier in the frequency range between 1.5 Hz and 21 kHz. It was designed and simulated in a 65-nm standard Complementary Metal-Oxide-Semiconductor process and 1 V power supply. Decreasing the low-cutoff frequency of amplifier to a few Hz in 65-nm technology with modest feedback capacitance is challenging. Thus, this low-cutoff frequency...
This paper presents a novel technique to achieve an effective capacitance, multiples of up to 40 times that of a capacitor embedded in electronic circuits thus minimizing the area of silicon die. The technique employed for multiplication is PMOS transistor based low-voltage cascode current mirroring consuming low-power. The proposed design, capable of achieving high multiplication factors, is simulated...
The KY converter, which features fast transient response, non-pulsating output current and simple structure, is a novel step-up topology to overcome the disadvantages of the traditional boost converter. Therefore, in this paper, based on the method of state-space averaging, the KY converter, including the inductor copper resistance and the output capacitor resistance is analyzed and modeled as a small-signal...
In this paper, a new realization of a fully-differential (F-D) first-order all-pass filter (APF) operating in current mode (CM) is presented. In the proposed F-D CM APF a single adjustable current amplifier (ACA) and two current followers (CFs) with non-unity gain are used as active building blocks. Considering the input intrinsic resistance of CFs as useful active filter parameter, the proposed filter...
This paper presents an ultra-low-power low-voltage Class-AB Fully Differential Operational Amplifier designed in 45-nm CMOS technology. The proposed circuit uses transistors operating in sub-threshold region for low-power and low-voltage operation. The proposed Op Amp offers an open-loop gain of 74.6 dB, 1 MHz unity gain frequency, 50-degrees Phase Margin, and 91.55 dB common-mode rejection ratio...
A CMOS amplifier with 124-dB dc gain and 92% rail-to-rail output swing is proposed in this paper. The proposed amplifier uses double gain-boosting technique, enabling triode-region operation in cascode output stage. The design is fabricated in a commercial 0.35-μm CMOS technology. The active chip area is 84 μm × 170 μm. Experimental results show that with the supplies of ±1 V, the high-gain region...
In this paper a novel multiple gain switched capacitor (SC) DC-DC converter circuit with eleven switches and two flying capacitors along with a filter capacitor is presented. This converter is capable of powering electronic devices at different voltages in the buck or boost mode. Since proposed SC topology is inductorless, these converters can achieve multiple gains either in buck or boost mode at...
In this paper, a new realization of a first-order voltage-mode (VM) All-Pass Filter (APF) using a grounded capacitor, three resistors, and a single Current Follower (CF) with non-unity gain is presented. The number of external resistors in the proposed VM APF can be reduced to two by considering the input intrinsic resistance of the CF as a useful active parameter. In comparison to the second-generation...
This paper describes the design and construction of an improved PID controller for a DC-DC buck converter working in Continuous Conduction Mode (CCM). The converter operates at a switching frequency of 1MHz. The lead-lag controller is first designed on the basis of classical theory of control systems using root-locus technique. The controller is then equivalently converted into a PID controller. The...
In this paper, we analyze the propagation of uncertainties in a programmable gain amplifier. The circuit is based on a superregenerative configuration and its gain is set by the duty-cycle of a digital signal. The uncertainty analysis allows for better component specifications in the circuit design, identifying the sources of uncertainties that play major role on the final gain uncertainty.
This paper presents a new gain stage based on the Replica gain enhancement method. The proposed gain stage operates 2.35 times faster than a similar size two-stage gain stage in the same precision, power consumption, and the same load capacitor. Proposed structure has been simulated by HSPICE software using level 49 parameters (BSIM3v3) in a typical 0.18µm CMOS technology. HSPICE simulation confirms...
A fully differential 144GHz CMOS amplifier has been demonstrated in 65nm CMOS. It validates a maximum 20dB power gain and has positive gain over 38GHz frequency range from 126GHz to 164GHz. With stacking circuit architecture, the amplifier can tolerate up to 2V supply without reliability concern. It also delivers over 5.7dBm saturated output power with PldB of 5dBm under a 2V supply. The amplifier...
This work demonstrates that the composite cascode differential stage, operating in the subthreshold region, can form the basis of a high-gain (110 dB), low-power op amp (27.8 μW). The circuit can be fabricated without adding a compensation capacitance. Advantages of this architecture include high voltage gain, low harmonic distortion, low quiescent current and power, and small chip area. These advantages...
Comparator based switched capacitor technique is a new topic because of its suitability of scaling and its inherent low power consumption. Since CBSC technique suffers from the overshoot due to the comparator delay, this paper gives a detailed analysis on the overshoot signal, and a common mode feedforward circuit is proposed to correct the overshoot error. A 10-bit 100 MS/s pseudo differential pipelined...
In this study, a CMOS current controlled current differencing buffered amplifier (C-CDBA) implementation is presented. Also, a novel first-order all-pass filter is proposed to show its advantages. Simulation results are in good agreement with the theoretical ones.
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
This paper discusses the application of thin-film inductors to thin-film-based LC filters. We fabricated a monolithic thin-film LC filter by using rf sputtering and dry etching techniques. The filter consists of thin-film inductors and thin-film capacitors fabricated on a common substrate. This filter was designed as a second-order low-pass filter having Chebyshev characteristics, with a cut-off frequency...
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