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The following topics are dealt with: low power delta-sigma analog to digital converter; body channel communication; high performance data converters; ESD protection for CMOS integrated circuits; sensors and MEMS; RF filters; microwave filters; power quality; biomedical circuits; UWB LNA and transmitter design; VLSI for arithmetic; adaptive signal processing; human machine interaction intelligent system;...
Two recently developed architectures, both applying an internal coupling of the quantization noise, are described. They allow higher-order noise shaping with high linearity and robust performance. Implemented examples of the proposed structures are described to verify their effectiveness.
Body sensor network and body area network are very attractive as the communication solution to the ubiquitous healthcare systems, portable audio/video systems, and interactive entertainment systems. Body channel communication, using the human body as the signal transmission medium, can achieve high speed communication with low energy consumption compared with the WPAN based solutions such as Zigbee,...
High-performance electronic systems use more and more use high-performance data converters for improving and shaping the architecture and opening new application perspectives. The current and future trend depends on old and new factors that include global economy, technology evolution and marketing. All these elements are driving forces and create new challenges for the designer that answer the requests...
A 12b 2 MS/s cyclic ADC achieves low power consumption with a single-ended rail-to-rail input signal range of 3.3 Vp-p. The proposed voltage reference scheme directly employing power supply voltages implements an offset voltage less than 1 mV without well-known calibration and trimming techniques. The prototype ADC in a 0.18 mum CMOS technology demonstrates the effective number of bits of 11.48 for...
This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8 V, 0.18 mum digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3 ps peak-to-peak) chip-level clock distribution is ensured by five-level balanced clock tree, implemented in low swing current-mode logic. The ADC block achieves...
This paper presents a flexible fully integrated self-calibrated quad-core 12-bit current-steering 180 nm CMOS DAC. Its novel architecture features multiple parallel sub-DAC unit cores. Their various combinations deliver smart flexibility in: performance, functionality, power management, design reuse, and smartness. The parallel sub-DAC units can be used together or separately to optimize the performance...
New trends in wireless communication systems require multi-standard coexistence and high data rates. In order to meet these requirements, we propose a reconfigurable baseband platform with coarse grained heterogeneous execution units and flexible interconnections, which are controlled by configuration information. In addition, we demonstrate the effectiveness of our approach in three sample implementations,...
Conventional Weaver receivers select the signal channel and reject the image. This paper offers a simple method making it possible to select either signal or image by a single LO frequency. As a result, the number of LO frequency locations can be reduced by half, thereby relaxing the RF integer-N PLL frequency synthesizer requirements.
A multi-pipeline dynamically reconfigurable system (MPRS) with coarse-grained processing elements is described in this paper. A systematic mapping method implemented by analyzing a dependence graph with reconfigurable variables (DGRV) based on an MPRS is proposed. The details of the systematic mapping processes are presented and the object functions of the automatic mapping are analyzed. With development...
Reed-Solomon (RS) codes can be found in many communication and digital storage applications. Among various decoding algorithms, algebraic soft-decision decoding (ASD) of RS codes can achieve very good performance with polynomial complexity. Interpolation is a major step of ASD algorithms. It has been shown that the architectures for interpolation with small multiplicities can achieve higher efficiency...
In this paper, we present a flexible high-throughput LDPC decoder architecture that can support different code rates and block sizes in wireless applications such as IEEE 802.11n, IEEE 802.16e, and IEEE 802.15.3c standards. Several flexible LDPC decoders have been presented in the literature but their throughput (less than 640 Mbps) is limited due to block-serial scheduling of the decoding computations...
In this paper, a cumulative electrostatic discharge (ESD) induced degradation of power-rail ESD clamp circuits in high-voltage (HV) CMOS/DMOS technologies was proposed. The IC which was verified by in-house test that it can pass Human-Body-Model (HBM) ESD 2 kV and Machine-Model (MM) ESD 200 V criteria, on the basis of test procedure described in JEDEC standards, was reported that it canpsilat pass...
This paper describes an ESD verification methodology that is applied at several points in the design process. By identifying ESD reliability hazards at each step in the design flow, the amount of redesign needed to address ESD reliability issues is greatly reduced. The checker efficiently computes power bus parasitic resistances, allowing it to be used during floor planning when the library is unavailable;...
New active ESD protection design for the interface circuits between separated power domains has been proposed and successfully verified in a 0.13-mum CMOS technology. The HBM and MM ESD robustness of the separated-power-domain interface circuits with the proposed active ESD protection design can achieve over 4 kV and 400 V, respectively.
In high voltage (HV) ICs, the latch-up immunity of HV devices is often referred to the TLP-measured holding voltage because the huge power generated from DC curve tracer can easily damage HV device during measurement. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25-mum 18-V bipolar CMOS DMOS (BCD) process to investigate the validity of TLP-measured snapback holding voltage to the device...
Moving object extraction from a video sequence plays an essential role for various machine vision applications such as video surveillance, traffic monitoring, and human motion analysis. There are two widely used methods for moving object extraction: the frame differencing method and the background subtraction method. Although the background subtraction method usually generates superior results to...
This paper presents the progress towards a fall recognition algorithm based on MEMS motion sensing data. A Micro Inertial Measurement Unit (muIMU) that is 66 mm times 20 mm times 20 mm in size is built. This unit consists of three dimensional MEMS accelerometers, gyroscopes, and a Bluetooth module. It records human motion information, and the database of FALL and NORMAL is formed. We propose principal...
This paper presents in details the architecture and most of RF front-end building blocks of a fully integrated passive radio frequency identification (RFID) transponder operating at UHF 902 MHz to 928 MHz. A novel architecture for the transponder IC and a new low power on-off keying (OOK) demodulator are proposed in this paper. For realizing the system, a low power CMOS full-wave rectifier achieving...
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