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We propose selective scaling of device footprint for 65 nm and beyond CMOS technologies. The benefits of selective scaling of device footprint are illustrated using an ultra-thin body (UTB) fully-depleted SOI (FD-SOI) transistor as an example. We study the effect of footprint scaling on device, circuit, and system level performance. A complete 2D device structure is modeled for the numerical analysis...
This paper presents a simple yet effective method to analyze process variations using statistics on manufacturing in-line data without assuming any explicit underlying model for process variations. Our method is based on a variant of principal component analysis and is able to reveal systematic variation patterns existing on a die-to-die and wafer-to-wafer level individually. The separation of die...
A quarter-rate CDR circuit is based on a dual-loop approach where sampling phases are generated by a phase-programmable PLL that is controlled by a digital DLL. Implemented in 65nm SOI CMOS, the chip occupies 0.03mm2 and consumes 1.8mW/Gb/s. Measurements confirm 40Gb/s operation with a BER <10-12 at a maximum frequency-offset of 400ppm. The phase relation between data and edge samples can be programmed...
A complementary LC-VCO is integrated in a 65nm SOI process and is statistically characterized on a 300mm wafer. Average center frequency is 67.9GHz and frequency tuning range is 6.14GHz or 9.05%. It achieves a phase noise of -106dBc/Hz at 10MHz offset and consumes 5.37mW from a 1.2V supply. The VCO yield is 94.7% for 70GHz operation.
A half-rate source-series terminated TX, operating at data-rates up to 16Gb/s, targets chip-to-chip on-board interconnects. The TX features a 4-tap FFE, tunable termination, and clock-cleanup circuitry for low duty-cycle distortion, and is capable of driving loads referenced to a variable termination voltage, including Gnd, VDD, and VDD/2. Implemented in 65nm SOI, it occupies an area of 230 times...
In this paper, the I/O structure described is based on a state of the art 65nm SOI technology designed for SRAM and logic applications (Leobandung et al, 2005). It is a twin-well partially depleted SOI (PDSOI) CMOS technology with gate oxide thicknesses of 1.05nm (SG) and 2.35nm (DG)
History effects in 65-nm partially-depleted silicon-on-insulator CMOS technology are systematically measured and characterized. The impact of various process adjustments on these effects is analyzed, and an optimization strategy is presented. Hardware data show >9% history effect changes is controllable with no loss of performance (e.g. speed and leakage), offering more flexibility in SOI circuit...
Deep CMOS technology requires more and more accurate and robust RF CMOS models (PSP, BSIM, EKV...) for circuit design, predictable down to millimetrique wave range. Because of their scalability, these models are the more convenient ones, their major drawback being the huge number of parameters to experimentally extract, which is costly and time consuming. Hence, whenever CMOS technology is under development,...
Today, measurement of 65 nm CMOS technology demonstrates Ft around 200 GHz and Fmax higher than 250 GHz as stated in G. Dambrine et al. (2005), which are clearly comparable to advanced commercially available 100 nm III-V HEMT or state-of-the-art SiGe HBT based in P. Chevalier et al. (2004). This increase allows new millimeter wave (MMW) applications on silicon. One of the success keys is then the...
A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations. A 7-pipe stage, 91 FO4, double-precision floating-point unit allows forwarding of dependent results after 6 cycles in most cases
We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit design are also discussed. It will be shown that PMOS and ring oscillator performance can be significantly enhanced by optimizing the transverse and lateral...
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting...
A thin SOI ground plane (GP) design is explored for CMOS application beyond 65nm generation node. The ground plane design is implemented using dopant implants at zero degree angle, in contrast to conventional halo implants, which are typically done at large implant angles. The large angle implants may become impracticable as neighboring devices are positioned closer to each other in an ultra-scaled...
An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS "stressors"). A stress memorization process and a tensile-stressed liner film are used to induce tensile strain in the NMOS (NMOS "stressors"). With optimization, the different...
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