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Recent progress in the fabrication of three-dimensional integrated circuits has opened up the possibility of exploiting this technology to alleviate performance and power related issues raised by interconnects in nanometer CMOS. Physical synthesis for three-dimensional integrated is substantially different from traditional planar integrated circuits due to the presence of additional constraints of...
This paper presents a new technique to improve performance of wide dynamic circuits by efficiently using the conditional keeper. PMOS transistor which is used to charge the dynamic node in the precharge phase is also used as a conditional keeper in the evaluation phase. The keeper functionality is merged in precharge PMOS. It is found that at same DC noise robustness; this technique gives 9% improvement...
A reduced supply voltage must be accompanied by a reduced threshold voltage, which makes this approach to power saving susceptible to process variation in transistor parameters, as well as resulting in increased subthreshold leakage. The paper propose a new adaptive body biasing scheme, based on a lookup table for independent control of multiple functional blocks on a chip, which controls leakage...
Programmable embedded systems are ubiquitous nowadays, and their number will even further increase with the emergence of Ambient Intelligence. One of the first challenges for embedded systems is mastering the increasing complexity of future Systems on Chip (SoC). The complexity will increase irremediably because the applications become more and more demanding and the algorithmic complexity grows exponentially...
The deep submicron (DSM) semiconductor technologies make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go to typical-case design methodologies, where designers are focusing on typical cases rather than worrying about very rare worst cases. In this paper, canary logic is proposed as a promising technique that enables the typical-case...
We present a technique for fault tolerance in prefix-based adders, and show its application by implementing a Kogge-Stone adder. The technique is based on the fact that an n-bit Kogge-Stone adder can be split into two independent n-bit Han-Carlson (HC) adders by augmenting an additional computation stage to the adder. The presence of single faults only affects one of these HC adders, thus we use a...
PSL supports property inheritance by verification units. The lack of formal semantics of the inherit operator is an obstacle to reduce the complexity of system design and verification. This paper presents a verification-layer specification assurance tool. Based on the component-based design methodology, we propose a principled organization of component specifications, and apply SAT solvers to verify...
Yield of nanometer-scale devices is increasingly challenging due to the increasing contribution of systematic defects that are affected by the product design itself. While inline inspection has been the conventional tool used to detect and isolate significant yield limiting mechanisms, there is a need to augment this information with the analysis of electrical test results obtained using electrical...
This paper presents the test results on the CMOS model symmetry and continuity characteristics between BSIM4 and BSIM5 from University of California at Berkeley. It is shown that the industry standard model BSIM4 has a series of the shortcomings of the continuity and symmetry, such as the charge, high-order current derivatives, and the trans-capacitances while new generation BSIM MOSFET compact model,...
Reduction in power consumption has been an important concern in low-power and high-performance systems. This paper addresses the problem of static voltage scaling in such systems which is a well studied technique. In this paper we present an optimal methodology for static voltage scaling. Previous techniques use path-based timing constraints in the system model which requires exponential runtime even...
In this paper, we propose a new circuit technique called self-timed regenerator (STR) to improve both speed and power for on-chip global interconnects. The proposed circuits are placed along global wires to compensate the loss in resistive wires and to amplify the effect of inductance in the wires to enable transmission line like behavior. For different wire widths, the number of STR and sizing of...
An important factor which greatly affects the power consumption and the delay of a circuit is the input capacitance of its gates. High input capacitances increase the power consumption as well as the time for charging and discharging the inputs. Current approaches address this problem either through gate-level only resynthesis and optimization, or indirectly through transistor-level synthesis aimed...
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation of both dynamic and leakage power, including the power dissipation due to emerging leakage mechanisms such as gate oxide tunneling, for partitioned arrays that deploy data-retaining sleep techniques for leakage reduction....
In this paper, we present an efficient algorithm to predict the probability distribution of the circuit delay while accounting for spatial correlations. We exploit the structure of the covariance matrix to decouple the correlated variables to independent ones in linear-time, as opposed to conventional techniques which have a cubic-time complexity. Furthermore, we present a closed-form expression for...
In this paper, we investigate the impact of process variations on future interconnect solutions based on single-walled carbon nanotubes (SWCNT) bundles. Leveraging an equivalent RLC model for SWCNT bundle interconnect, we calculate the relative impact of ten potential sources of variation in SWCNT bundle interconnect on resistance, capacitance, inductance, and delay. We compare the relative impact...
This paper presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in fading channels. The proposed scheme pre-analyzes each received data frame to estimate the maximum number of necessary iterations for the frame convergence. The results are then used to dynamically adjust decoder frequency and switch between multiple-voltage...
Ever since process technology moved below 90nm, variability in manufacturing has been increasingly significant in the digital design flow; moving from a secondary issue to a primary design flow consideration. Initially addressed by performing verification under a couple process corners and later expanding to many corners and OCV, variability is adding excessive complexity to the digital design flow...
A thermal-aware placement is proposed for FPGAs to reduce the peak temperature and maximum on-chip gradient temperature. A new thermal cost is defined for the simulation annealing core of the placer based on the electrostatic charge model instead of extracting temperature profile in each simulation iteration. The thermal cost change rather than its actual value is derived to keep the runtime complexity...
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