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In this paper, two low-power architectures for display processing specifically for head-mounted displays are presented. The proposed solutions are implemented in an FPGA-based platform and are analyzed in terms of power consumption, area, flexibility for further improvement. The results are compared with an existing hardware solution.
In recent years, the low power technology has brought up a great impact on portable electronic devices. As for the mobile device, the low-power circuit design becomes the primary issue. At present, TFT LCD has been widely used in handheld mobile devices. In terms of the overall system power consumption, TFT LCD power consumes 20%~45% of the total system power depletion due to different applications...
A novel framework for supporting architecture-level exploration for heterogeneous FPGA devices is introduced. This framework, named NAROUTO, is based on open-source tools in order to support further extensions and improvements. As compared to previous works, the introduced framework provides higher flexibility for application implementation, while it can also evaluate power/energy consumption. Experimental...
Field Programmable Gate Arrays (FPGA) are flexible, so they are commonly used in many high speed applications. However, power constraints are the most important limiting factors while implementing high speed adaptable applications. This work addresses the optimization of the execution time and power consumption. We propose a new design methodology by extending Algorithm-Architecture-Adequacy (AAA)...
Power efficient solution is essential for the portable electronic system. This paper presents an FPFA based embedded system for low power message display. Scanning technique is used to minimize the power. Experiment is conducted on 30 seven segments where an FPGA based intelligent controller scans all the display elements continuously at a certain speed to ensure only one display unit is on and other...
In this paper we propose an efficient, low power algorithm and its co-designed VLSI architecture for fractional-pel motion estimation (FME) in H.264/AVC. Our fractional-pel motion estimator uses a simplified FIR filter for half-pel interpolation. Usage of this filter reduces the required number of computations and the memory size and bandwidth for half-pel interpolation. Our simulations compare our...
A generalized power efficient clock distribution technique for the input registers of the polyphase comb decimation filter is presented. A general form of the proposed technique is developed for any integer decimation factor. The Spartan3 low power FPGAs family is used to implement both proposed and conventional comb filters. From the implementation results it is shown that, applying the proposed...
We report a two-dimensional (2D) pixel block scanning architecture for image segmentation by segment growing. This architecture can optimize processing speed, power consumption, and circuit area by modifying size and shape of the pixel block. Real-time processing can be maintained by using additional the two important techniques of (i) boundary-scan of the grown segment only, (ii) continued block-internal...
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Two major gate level techniques are introduced in order to reduce the power consumption, namely the pipeline technique (with some variants) and the use of embedded RAM blocks instead of general purpose logic elements. Power...
Power optimization has become one of the most challenging design objectives of modern digital systems. Although FPGAs are more and more used, they are however still considered as power inefficient compared to standard-cell or full-custom technologies. New dedicated design approaches are thus needed to reduce this gap. In this paper, we address low-power design on FPGA through a dedicated High-Level...
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGA-based systems. The clock-gating techniques are used to reduce the total power of the system. To achieve this, we reduce clock power consumption of the system by switching-off the clock signal for the parts of system that are not used. The system presented in this paper is based on the main...
Quaternary logic has shown to be a promising alternative for implementing FPGAs, since voltage mode quaternary circuits can reduce the circuits' cost and at the same time reduce its power consumption. In this paper, we study the implementation of circuits in quaternary logic. To obtain cost-effective implementations of quaternary circuits, we propose a mapping from binary to quaternary circuits based...
In this paper, a new high-speed low-power pipelined Add Select-Compare (AS-C) method and its architecture is proposed for a high throughput Viterbi Decoder (VD). The proposed pipelined AS-C unit breaks the Add-Compare-Select (ACS) recursion of the close-loop with a small area overhead, and uses the pipeline to improve the speed power of VD. After we verified the function and made the platform by FPGA,...
Great advancements in the electronics technology are making possible applications that were considered science fiction only few decades ago. Increases in packaging density of electronic devices, shrinking of physical weight and volume, and accelerated drop in prices, have all helped for the realization of ubiquitous computing using mobile and embedded electronic devices for everyday use. However,...
We propose a microphone array network that realizes ubiquitous sound acquisition. Nodes with 16 microphones are connected to form a large sound acquisition system that carries out voice activity detection (VAD), sound source localization and sound source separation. The three operations are distributed among nodes using network. Because the VAD is implemented to manage power consumption, the system...
In wireless sensor network nodes all tasks are controlled and scheduled by the CPU of the node. It is activated repeatedly from its low-power sleep mode for e.g., measurements and communications tasks. The periodic wake-ups cause a high overhead in power consumption. This problem can be solved by supplementing the CPU with additional modules which autonomously execute selected tasks to enable the...
A firewall's complexity and processing time is known to increase with the size of its rule set. Empirical studies show that as the rule set grows larger, power consumption and delay time for processing IP Packets particularly on Hardware firewalls increases extremely, and, therefore the performance of the firewall decreases proportionally. This paper present a new FPGA (field programmable gate arrays)...
Field programmable gate arrays (FPGAs) allow the same silicon implementation to be programmed or reprogrammed for a variety of applications. It provides low NRE (non-recurring engineering) cost and short time to market. As CMOS technology continue to scale down to nanometer, increased power consumption and worsened process variation become crucial constraints for FPGAs. The survey reviews the process...
This paper presents a low-power FPGA with multiple supply voltages. In the proposed FPGA, the supply voltage of each logic block is self-adaptive to the workload, data path and temperature to minimize the power consumption without system performance degradation. In the self-adaptive voltage control scheme, features of the asynchronous architecture are exploited. The data arrival of the asynchronous...
Energy-performance tunable circuits enable the user to adjust the energy and performance of a chip after fabrication to suite the particular application, thus increase the overall power efficiency of the chip. Two tunable interconnect architectures are proposed. Pseudo-static interconnect achieves the same performance as static interconnect while consuming only 65% as much energy and provides 2X wider...
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