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In this study, a micro tensile test method that can measure the interface strength of a grain boundary has been developed by applying an EBSD (Electron Back-Scatter Diffraction) method and a FIB (Focused Ion Beam) system, and it was applied to evaluate the effect of the crystallinity of a grain boundary on the strength of electroplated copper thin films quantitatively. The position and crystallinity...
In this paper, anodic aluminum oxide (AAO) is introduced as a potential new material for making interposers, and a low cost process for building high density interposers is demonstrated. Hard anodic process was used to create thick anodic aluminum oxide (AAO) films containing high density vertical nanopores on aluminum substrates. Silicon dioxide (SiO2) deposition by plasma enhanced chemical vapor...
Recent advancement in chip design which made it possible to achieve more functionality in a smaller package means that the silicon die design needs to be compact and multi layered. One particular case which often caused difficulty to failure analysts was the Common Mode Filter (CMF) devices packed in the multi-leads, XDFN package. The device comes with an integrated ESD protection. Differential signaling...
The SnPb solder ball was reflowed on the Cu film in a flow of reducing gas, and the reactive spreading process was in situ recorded by a CCD camera. On the thicker Cu films, it was observed that dewetting did not happen even if the Cu6Sn5 intermetallic compounds spalled into the liquid solder. However, on the thinner Cu films, dewetting would occur when the liquid SnPb solder consumed the underneath...
The sputter-deposited Cu thin film, coated with a thinner gold layer, was prepared into the butterfly pattern with alternating zones beween Cu thin film and Si. The eutectic SnPb solder balls with different sizes were reflowed on the butterfly pattern. As a result, the liquid solder would be selectively retained on the Au/Cu film zones. At the same time, under the energy minimization control, the...
Curtaining effect and sample thickness constraints are always the key factors of limiting the use of ex-situ lift-out technique in advanced semiconductor device analysis. Over the years, in-situ lift-out technique has gradually replaced ex-situ lift-out because it offers greater advantages that can overcome the mentioned problems. A novel technique has been developed to prepare ultra-thin TEM specimens...
The chemical interaction of Al and Mn deposited on Ru thin films for use as copper diffusion barrier layers are assessed in-situ using x-ray photoelectron spectroscopy (XPS). Thin (∼1–2 nm) Al and Mn films were separately deposited on 3 nm Ru liner layers on SiO2, and both Al/Ru/SiO2 and Mn/Ru/SiO2 structures were subsequently thermally annealed. Results indicate the diffusion of both metals through...
In this work, a novel single layer CoMo alloy film is investigated as an excellent adhesion/diffusion barrier to copper metallization. The ultrathin (<3nm) CoMo film can withstand 400°C/30min annealing on the ULK(k =2.25) and the electrical barrier properties on the p-cap SiO2 structure for the Cu/CoMo can be even better than the Cu/Ta/TaN structure. The CMP of the CoMo film are studied and the...
The SnPb solder ball was reflowed on the Cu film in a flow of reducing gas, and the reactive spreading process was in situ recorded by a CCD camera. On the thicker Cu films, it was observed that dewetting did not happen even if the Cu6Sn5 intermetallic compounds spalled into the liquid solder. However, on the thinner Cu films, dewetting would occur when the liquid SnPb solder consumed the underneath...
The sputter-deposited Cu thin film, coated with a thinner gold layer, was prepared into the butterfly pattern with alternating zones beween Cu thin film and Si. The eutectic SnPb solder balls with different sizes were reflowed on the butterfly pattern. As a result, the liquid solder would be selectively retained on the Au/Cu film zones. At the same time, under the energy minimization control, the...
The degradation process of the crystallographic quality of copper thin films, which are used for interconnections and micro bumps for 3D integration, during electromigration and stress-induced migration tests is dominated by the diffusion along grain boundaries and the diffusion constant of copper varies drastically depending on the crystallinity of the films. The degradation process was visualized...
Polyvinylidene fluoride (PVDF) has a strong piezoelectricity. With the piezoelectric coefficient of poled thin films as large as 6–7 pC/N, PVDF is becoming a popular material for the sensors and energy harvesting. However, the fabrication process of PVDF is a big challenge due to the physical and chemical properties of PVDF. In this paper, a spiral-shaped PVDF cantilever is fabricated to harvest vibration...
Growth and characterization of graphene grown using copper foils as well as copper films on silicon dioxide on silicon substrates were performed. Kinetics of growth and effective activation energy for the graphene synthesis will be discussed for the surface catalytic synthesis of graphene. Conditions for large-scale synthesis of monolayer graphene will be addressed in this talk. Wafer-scale graphene...
To realize high density 3D packaging, various types of interposer including through vias are developed. Although the interposer should have a high wiring density not only horizontally but also vertically, the ability of the conventional interposers to provide high density through vias with a low cost is still quite limited. Copper-filled anodic aluminum oxide has been studied as an alternative interposer...
Smart phone and tablet devices are making our lives more convenient, informative, and enjoyable. Underpinning the development of these devices are semiconductor package technologies, which are being pushed to the limit. The Controlled Collapse Chip Connection (C4) process had been the major packaging technology for flip chip devices, which provides more I/Os and faster communication speeds. However,...
An overview is given of developments in unit-process and process-integration technology enabling the realization of through-silicon vias (TSVs) for 3D chip stacking. TSVs are expected to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency [1–3]. The fabrication sequences for forming TSVs in the middle of the line (via-middle approach)...
This paper will focus on 300mm etch and CVD technologies for via reveal (VR) processing. Data on silicon etching will show that etch rates >5μm/min, with uniformity ±2.5% and selectivity to the liner oxide around ∼200:1 can be achieved on bonded TSV wafers. A novel end-point detection method will also be presented allowing control of the reveal height. The ability to tune the uniformity from centre...
For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called “chip-level TSV integration”) was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection...
In this paper, we focus on a method to evaluate and to optimize the die shift that occurs during epoxy molding for embedded wafer level technology (eWLB), basically by adjusting the adhesion level of silicon dies on top of the temporary carrier support. Here, a stress-free 70µm thick silicon dies were prepared using dicing before grinding process (DBG). Then a total of 495 dies were placed on a 8inch...
In this study, we used electroless deposition of NiP, NiWP on p-type Si as the barrier layer to prevent the diffusion of Cu into Si. We added different amount of W into the layer, wt% is 11.89% (NiWP-1) and 25.36% (NiWP-2). After annealed at various temperatures, thermal stability of the Si/Ni(W)P/Cu layers were evaluated by measuring the changes of resistance of the samples, using four-point probe...
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