The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, the major methodologies proposed in the last years to speed-up the synthesis of radio-frequency integrated circuits blocks are overviewed. The challenges to automate this task are discussed, and, to avoid non-systematic iterations between circuit and layout design steps, the architecture of an innovative solution is proposed. The proposed tool exploits the full capabilities of most...
This paper proposes a free and complete EDA framework for teaching CMOS full-custom design of mixed-signal integrated circuits. The presented set of EDA tools and associated physical design kit should allow students to gain hands-on experience on schematic entry, both at system and circuit levels, HDL system simulation and block specification, automatic circuit optimization, PCell-based netlist-driven...
Substrate noise coupling due to minority carriers propagation in smart power integrated circuit becomes a critical issue specially for high voltage applications. Computer-Aided-Design modeling methodology for substrate parasitic-immune design was introduced. It is based on constructing a 3D substrate equivalent network. The substrate equivalent network consists of models of diodes and resistors that...
Electromagnetic Interference (EMI) becomes one of emerging issues for recent designs because LSI-Package-Board system is getting larger and more complicated. There are difficulties in simulating and understanding causes of EMI-noise. However there are few papers discussing simulation methods and root cause analyses for EMI-noise issues. This paper proposes a new efficient and quick method based on...
This paper proposes a methodology to design radiation-hardened ICs, suitable for space applications and high-energy physics experiments. The miniaturization of ICs has brought an increase of circuit logic errors due to radiation, also at ground level. The increased complexity of IC design due to technology scaling requires new tools to design rad-hard circuits. In this paper, we propose a design tool...
In this paper, a proposed methodology to identify the substrate coupling effects in smart power integrated circuits is presented. This methodology is based on a tool called AUTOMICS to extract substrate parasitic network. This network comprises diodes and resistors that are able to maintain the continuity of minority carrier concentration. The contribution of minority carriers in the substrate noise...
Three dimensional integrated circuits (3DICs) allow for increased device density and performance while also facilitating heterogeneous integration of different functionalities into one 3D stack. These features can be leveraged in the implementation of innovative multi-purpose 3DICs for aerospace applications which often require high performance multi-functional chips for a variety of applications...
On-chip EM modeling at mm-wave frequencies requires design methods that incorporate the layout and verification macros of IC EDA tools with parameterized EM CAD. We propose a novel, flexible design flow for 3D EM modeling of BEOL structures that allows for parameterized design of BEOL structures using Pcell elements as seed, thereby reducing the time required to generate the full simulation model...
In this work, a fully automated process emulation is presented. Starting from industrial standard gdsII mask files a user friendly and fast way to create TCAD ready models has been realized. A three step approach is used. The creation of virtual layers to allow for logical operation based on masks is shown. Then the geometrical and dopant profile instantiation is carried out. Third the mesh generation...
High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach based on transistor layout is presented that is compatible with parasitic substrate noise propagation in Smart Power ICs. The results of the model...
In smart power IC technology, low and high voltage circuits are integrated on the same substrate. The commutation of the high voltage circuits can induce substrate parasitic currents which can severely disturb the operation of the low voltage circuits. The parasitic currents due to minority carriers in the high voltage technology can be significantly high. However, the minority carrier propagation...
As technology reaches atomic scales, circuit performance is significantly affected by the variability of electrical properties within transistors such as random dopant fluctuation (RDF), line edge roughness (LER), and layout driven variations. This increases pressure on designers to find methodologies that more effectively mitigate the impact of device parameter fluctuations and improve circuit performance...
In this paper, we discuss the implementation of Open Source CAD (Oscad) [1], a complete EDA tool for Electronics and Electrical engineers. The paper illustrates the use of Oscad for circuit design, simulation and PCB design. It also gives implementation details of an in-house developed circuit simulator, Scilab based Mini Circuit Simulator (SMCSim), available in Oscad. The simulator can provide the...
The aim of this contribution is to show why sources of non-idealities are actually a concept of reason in order to define tradeoffs in the design of analog circuits. A tradeoff is commonly picked up from an analytical design-model, which tries to explain a given phenomenon under study by using physical theories underlying the role of non-idealities in the design of accurate analog-circuits. Since...
With the widespread adoption of design for manufacturing techniques and design and process co-optimization as well as the increase in the complexity of the processes to manufacture integrated circuits there is pressing need in finding quickly to calibrate yet accurate and high performing methods to identify layout topologies which may cause yield loss. While full-based simulations provide the most...
This paper presents a switched-capacitor simulator, optimized for fast computations. Two CAD tools are implemented in order to perform Monte-Carlo simulations, to identify sensitive parasitic coupling prior to layout and to rapidly verify parasitic coupling from an existing layout. Simulation results and measurements on a ΣΔ ADC are compared to validate the tools1.
This paper presents a full simulation methodology dedicated to the ESD primitive devices development in High Voltage technology. This workflow based on layout generation, 2D, 3D and mixed-mode TCAD simulations and SPICE simulations provide robust devices sustaining ESD stress tests.
For advanced fabrication technology nodes, novel single-event related failures are being observed. This paper details efforts to use 3D TCAD simulations to model these failure mechanisms and develop mitigation techniques for flip-flop designs. Simulation, as well as experimental, results are used to show validity of such an approach for future CMOS technologies.
The mathematical modeling and analysis of various CPW discontinuities are presented in this paper. Simulations of these discontinuities are done through ADS and its electrical equivalent parameters are evaluated through MATLAB programming (M-file) for open, short and GAP. And compared with closed form relations. Various discontinuities analyzed are open end, short, step, GAP, bend. The analysis is...
Circuit-level simulations predict increased vulnerability of flip-flop designs and increased occurrence of single-event upsets in advanced technologies due to multi-node charge collection from single-ion strikes. This trend is examined by simulating 3D models of the flip-flops in a terrestrial neutron environment with Monte-Carlo simulations of charge generation in several technology generations.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.