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With the exponentially increasing capacity demands anticipated in next generation wireless networks, densifying the network using cmW and mmW small cells supporting high bandwidths is seen to be the trend in 5G networks. Such ultra-dense deployment of cells would also lead to a higher amount of power consumption, from the UE and network perspective, due to the increased measurement requirements and...
Practical considerations for future supercomputer designs will impose limits on both instantaneous power consumption and total energy consumption. Working within these constraints while providing the maximum possible performance, application developers will need to optimize their code for speed alongside power and energy concerns. This paper analyzes the effectiveness of several code optimizations...
For a standalone Fall Detection system based on computer vision we want to obtain a low power architecture to meet the real time processing, power consumption, energy constraints which also satisfy the high performance in recognition, and accuracy. In this paper, we present the different architecture explorations for Fall Detection system implemented on heterogeneous platform as Zynq-7000 AP SoC platform...
Many-core architectures are playing an important role in the HPC systems. But they are giving high performance at the cost of a great electrical power consumption. On Tianhe-2 supercomputer, the Xeon Phi many-core processors contribute nearly 80% of the system power. Power models are important to guide the design of dynamic power management (DPM) algorithms by predicting the power consumption with...
Small Cells are under extensive investigation as a potential solution to meet the increasing capacity demand due to ever growing data traffic over cellular networks. The architecture of small cells is still under discussion, various architectures have been proposed based on potential use cases. One of the most important use cases is to deploy small cells on a different frequency than that of the macro...
Heterogeneous computing using Graphic Processing Units (GPUs) has become an attractive computing model given the available scale of data-parallel performance and programming standards such as OpenCL. However, given the energy issues present with GPUs, some devices can exhaust power budgets quickly. Better solutions are needed to effectively exploit the power efficiency available on heterogeneous systems...
Dynamic Voltage Frequency Scaling (DVFS) has been the tool of choice for balancing power and performance in high-performance computing (HPC). With the introduction of Intel's Sandy Bridge family of processors, researchers now have a far more attractive option: user-specified, dynamic, hardware-enforced processor power bounds. In this paper we provide a first look at this technology in the HPC environment...
The importance of deploying energy efficient networks has vastly increased due to the rapidly growing nature of power consumption of ICT industry. This requires redesign of networks or modification to existing networks that could prove to be energy efficient. In this paper, two telephone networks namely traditional Public-Switched Telephone Network (PSTN) and Voice over Internet Protocol (VoIP), are...
Autonomous weather monitoring applications, especially the distributed ones, implies low power consumption both for sensors and computing/storage facilities. Making the autonomous system more efficient requires optimizing consumption for the computing and storage facilities are they require more energy to function than the sensors. Modern embedded systems are a solution, as they have to continuously...
The paper presents a distributed power consumption measurement system using ZigBee based wireless point of load power meters. The software architecture of the system is based the D-Bus inter-process communication solution. It is shown in the paper that our D-Bus based solution is better from the point of view of reliability and programming language support than the widely used JAVA based OSGi framework...
Power-constrained systems, such as RF-powered smart cards are gaining increased significance in the embedded system's domain. These systems are highly susceptible to supply voltage drops caused by power peak regions that impact on the system stability. Power profile flattening mechanisms have emerged as an effective power peak countermeasure to enhance system reliability. In this paper we present...
Power optimization has become one of the most challenging design objectives of modern digital systems. Although FPGAs are more and more used, they are however still considered as power inefficient compared to standard-cell or full-custom technologies. New dedicated design approaches are thus needed to reduce this gap. In this paper, we address low-power design on FPGA through a dedicated High-Level...
An 8-core SPARC64™ VIIIfx processor is fabricated in a 45nm CMOS process and achieves a peak performance of 128GFLOPS. Measured results show that the processor consumes only 58W of power when executing a maximum power program. Fine-grained power analysis was used to tune the micro-architecture for low power consumption, and circuit-level low-power techniques were developed. Water cooling and supply...
The power and reliability of communication are important factors in the design of wireless sensor networks. This paper examines the use of a shortened Reed-Solomon code for power reduction in patient-monitoring application Wireless Body Area Network. The implementations of the scheme on an 8-bit micro-controller and on an FPGA are presented. The paper compares the energy consumption of the designs...
As the market for mobile architectures continues its rapid growth, it has become increasingly important to understand and optimize the power consumption of these battery-driven devices. While energy consumption has been heavily explored, there is one critical factor that is often overlooked - the end user. Ultimately, the energy consumption of a mobile architecture is defined by user activity. In...
Multiprocessor architectures are becoming popular in both desktop and mobile processors. Among multiprocessor architectures, asymmetric architectures show promise in saving energy and power. However, the performance and energy consumption behavior of asymmetric multiprocessors with desktop-oriented multithreaded applications has not been studied widely. In this study, we measure performance and power...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
A low power reconfigurable DCT architecture is proposed, which can be run at three transform precision levels for different demands. Using the character of energy distribution of the DCT matrix after 2D DCT operation, we selected the best DCT bases which achieve considerable power reduction in DCT operation with minimum image quality degradation. The reconfigurable architecture can achieve power saving...
This paper presents a distributed fermat-point range estimation strategy, which is important in the moving sensor localization applications. The fermat-point is defined as a point which minimizes the sum of distances from three sensors inside a triangle. This point is indeed at the trianglepsilas center of gravity. We solve the problems of large errors and poor performance in the bounding box algorithm...
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