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A 12-GS/s 5-bit time-interleaved flash ADC is realized in 65-nm CMOS. The design utilizes a background timing skew calibration technique to improve dynamic performance, and comparator offset calibration to reduce power dissipation. The experimental prototype achieves an SNDR of 25.1 dB at Nyquist and 27.5 dB for low frequency inputs. The circuit occupies an active area of 0.44 mm2 and consumes 81...
This paper describes a 64-entry × 32b 1-read, 1-write ported register file with measured 8.3GHz operation consuming 83mW, fabricated in 1.0V 32nm CMOS. Contention-free shared keeper circuits combined with variation tolerant dual-ended transmission gate write memory cells enable 300mV Vcc-min reduction and measured scalable near-threshold voltage operation to 340mV with energy efficiency of 550GOPS/W.
We propose an RF-detector-less carrier leakage suppressor for a WiMAX transmitter. The proposed circuit directly detects the DC offset of a transmitter path and minimizes it, thus reducing carrier leakage. The correct DC-offset feedback to a baseband is achieved by performing an absolute offset comparison after the general binary search technique. The suppressor is integrated in the direct-conversion...
A fully-integrated 60-GHz transceiver utilizing analog FSK modulation/demodulation to replace baseband processor has been demonstrated. Employing a discriminator with automatic adjustment and a folded dipole antenna pair (5-dBi gain for each), the transceiver achieves > 1Gb/s data transmission over 1 meter with BER <; 10-12 while consuming a total power of 500 mW.
This paper demonstrates for the first time quantitative performance advantages of a zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T) with write-back schemes, which was previously recognized as the most area-efficient cell under large σVTH/VDD conditions. Since Z8T uses only 1T for each decoupled read-port, faster 2T differential sensing (D2S) can be implemented within...
A 60GHz CMOS multichannel wireless repeater, which converts digital data and millimeter-wave pulses without applying signal processing, is proposed for high-speed communication. A chip containing three repeaters operating at 60.48GHz, 62.64GHz and 64.8GHz frequency bands is fabricated using a 90nm CMOS process. Each channel has a 1Gbps data rate with power consumptions of 51mW and 116mW in the transmitter...
We propose circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage (Vddmin). Active bitline equalizing technique improves the write margin whenever a write-disturb occurs. This technique is applicable for both synchronous and asynchronous clock frequencies between ports. We designed and fabricated a 256 kb DP-SRAM macro using 28-nm low-power CMOS technology and achieved...
A per-core clock generator for the eight-core POWER7™ processor is implemented with a digital PLL. This frequency generator is capable of smooth, controlled frequency slewing, minimizing the impact of di/dt. Frequency can be dynamically adjusted while the clock is running, and without skipping any cycles, thus enabling aggressive power management techniques.
A MIMO chip for 3GPP-LTE standard and beyond is described. The chip implements sphere decoding algorithm with 16-core architecture. The chip is flexible to support multiple configurations: antenna arrays from 2×2 to 8×8, modulations from BPSK to 64QAM, FFT sizes from 128 to 2048 and hard/soft outputs. The chip dissipates 5.8mW for the 3GPP-LTE standard in 3.35mm2 area in 65nm CMOS.
An on-chip transformer-based digital isolator for intelligent power management (IPM) systems is proposed. It greatly reduces the number of chips in IPM systems by allowing integration of isolators in a CMOS chip together with MPUs or gate drivers. With a proposed pulse generation / detection scheme that enables a 5V standard CMOS transistor to utilize GHz-band signals, transformer area is reduced...
This paper presents a dual-path fully-overlapped QC-LDPC decoder for the WiMAX system. Each phase scans nonzero sub-matrices two by two in block row-wise order, and two phases are fully overlapped. It reduces memory accesses by 24.3-48.8%, and takes only 48-54 clock cycles per iteration. It is fabricated in SMIC 0.13 μm 1P8M CMOS process, which occupies 4.84 mm2, attains 847-955 Mb/s, and consumes...
This paper presents a non-contact memory card and a host employing simultaneous data and power transmission through inductive coupling. Nested clover-shaped data coils are proposed for reducing interference from a power link. The host wirelessly tracks current consumption of the card and adjusts transmit power to improve power transfer efficiency. The prototype is implemented in 65nm CMOS. It achieves...
A technique for in-situ measurement of process variation in deep trench capacitance, bitline capacitance, and device threshold voltage in embedded DRAM arrays is presented. The technique is used to directly measure the parameter statistics in two product representative 45-nm SOI eDRAM arrays.
An energy-efficient reconfigurable distributed-arithmetic FIR filter for multi-mode wireless communication is fabricated in 7M1P 90nm CMOS and occupies 1.5mm2. A 6-way parallel, 2-way time-multiplexed architecture with circuits for memory offset binary coding and memory partitioning enable input wordlength and tap configurability with 1-190MSample/s throughput and 10-130mW total power measured at...
A novel DRAM architecture with an ultra-high bandwidth is proposed for high throughput computing. The proposed architecture employs three techniques: 1) five-stage pipelined 16-DRAM cores, 2) an early bar write scheme for an 8-ns cycle array operation, and 3) a 16-Gbit/s I/O circuit on each of 32 through-silicon-via pairs/DRAM core. We conducted a circuit simulation assuming a 45-nm 1-Gbit chip and...
A quad-band 2.5G receiver integrates the front-end SAW filters, the LNA matching, as well as the RF baluns, achieving a typical sensitivity of close to -111dBm. Utilizing an arrangement of only four baseband capacitors and MOS switches driven by 4-phase 25% duty-cycle clocks, high-Q BPF's are realized to attenuate the 0dBm out-of-band blocker. The SAW-less receiver draws 55mA from the battery, and...
An 8-core SPARC64™ VIIIfx processor is fabricated in a 45nm CMOS process and achieves a peak performance of 128GFLOPS. Measured results show that the processor consumes only 58W of power when executing a maximum power program. Fine-grained power analysis was used to tune the micro-architecture for low power consumption, and circuit-level low-power techniques were developed. Water cooling and supply...
Lincroft, the next generation Intel® ATOM™ processor based SoC specifically designed for smartphones, is fabricated in 45 nm Hi-K metal gate CMOS. As part of the extensive low power methodology, the chip is divided into numerous power domains with on die distributed powergates to reduce both active and standby power. Measured data shows upto 50X reduction in standby power. Silicon data shows dramatically...
A down-converter insensitive to 2nd and 3rd harmonics and a digital assisting circuit that cancels residual sensitivity due to device mismatches are proposed. Measured 2nd and 3rd harmonic rejection ratios of over 60 dB are achieved. This performance allows a simple RF filter, and it is effective to reduce the die size.
This paper presents fast 10-ns read/write cycle FeRAM with small 0.35μm2 cell using highly reliable large ferroelectric capacitor of 0.145μm2 and with highly compatible process with logic-LSI.
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