The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Three-dimensional Field Programmable Gate Arrays (3D FPGAs) represent a viable alternative to overcome challenges of integration complexity in modern embedded systems. Mapping applications into 3D FPGAs requires a set of accompanying suite of Computer-Aided Design (CAD) tools. One of critical issue of a 3D FPGA-based implementation is the quality and efficiency of associated CAD algorithms. In this...
Newly-available spatial architectures to accelerate finite-automata processing have spurred research and development on novel automata-based applications. However, spatial automata processing architecture research is lacking, because of a lack of automata optimization and place-and-route tools. To solve this issue, we propose a new, open-source toolchain–Automata-to-Routing (ATR)–that enables design-space...
Although it is possible to design and manufacture MPSoCs with hundreds of processors, there is still a gap in the ability to debug hardware, software, and applications for such chips. Current state-of-the-art works related to MPSoC debugging suffer from poor integration, scalability in data storage, and simple graphical data representation. This work proposes a modular debugging framework to aid the...
This paper presents XL-STaGe, a cross-layer tool for traffic-inclusive directed acyclic graph generation and implementation. In contrast to other graph-generation tools which focus on high-level DAG models, XL-STaGe consists of a set of processes that generate the task-graphs as well as a detailed process model for each node in each graph. The tool is highly customizable, with many parameters that...
Substations design is a fundamental engineering component in power network construction. The benefits obtained for having adequate tools and design systems are related mainly to cost savings, reduction of construction problems and faster throughput of projects. In this paper we propose an approach based on three dimensional building blocks to construct virtual substations. The building blocks can...
In this paper, we propose a 2D and 3D interconnect network based on a Mesh-of-Clusters (MoC) topology for the implementation of an efficient Field Programmable Gate Arrays (FPGA) architecture. Proposed MoC-based FPGA architecture presents a new hierarchical Switch Box (SBs) and depopulated intra-cluster interconnect based on the Butterfly-Fat-Tree (BFT) topology. Long routing wires which span multiple...
In this paper, we propose a 2D and 3D interconnect network based on a Mesh-of-Clusters (MoC) topology for the implementation of an efficient Field Programmable Gate Arrays (FPGA) architecture. Proposed MoC-based FPGA architecture presents a new hierarchical Switch Box (SBs) and depopulated intra-cluster interconnect based on the Butterfly-Fat-Tree (BFT) topology. Long routing wires which span multiple...
In today's competitive market, a company's success is strongly dependent on delivering sophisticated and state-of-the-art IPs prior to their competitors. To take a short cut, a company may resort to reverse engineering or pirating their competitor's IP. In this paper, we examine the feasibility of extracting the design of a secure IP from one technology and using it in another. In particular, we start...
In recent years there has been a great interest in High Level Synthesis (HLS) CAD tools to raise the level of design abstraction, reduce design time, rapidly explore the design space and fully exploit the multi-million gate heterogeneous hardware platforms provided by dramatic improvements in integrated circuits. Open Computing Language (OpenCL) is a well-known standard for heterogeneous computing...
The digital signal processing system design consists in four synthesis phases which concern the processing, the control, the memory and the communication units. Today, many tools enables us to produce the processing unit. However, in many applications, the hardware solution may be challenged by the number and complexity of memories. This paper proposes a design methodology of the memory units for...
In the past engineering design would focus on in-service requirements such as functional and strength requirements. Today, design must also consider stringent environmental requirements and the handling of products after their “death.” Sustainable design requires that designers consider the environmental consequences of product creation, use, and after death. In all these three phases, product designers...
This paper presents the implementation of a complete fingerprint biometric cryptosystem in a Field Programmable Gate Array (FPGA). This is possible thanks to the use of a novel fingerprint feature, named QFingerMap, which is binary, length-fixed, and ordered. Security of Authentication on FPGA is further improved because information stored is protected due to the design of a cryptosystem based on...
This paper presents the design of a prototype for a wearable device that implements a recognition system based on in-air signature into a FPGA that receives data from a 3-axis accelerometer. The Dynamic Time Warping (DTW) algorithm has been analyzed and simplified to reduce the complexity of the hardware architecture that implements the matching in the FPGA. Despite simplification, accuracy of the...
A 'natural' way of describing an algorithm is as a data flow. When synthesizing hardware a lot of design effort can be expended on details of mapping this into clock cycles. However there are several good reasons - not least the maturity of Electronic Design Automation (EDA) tools - for implementing circuits synchronously. This paper describes: a) an approach to transform an asynchronous dataflow...
We present a complete EDA tool that quantifies the susceptibility of each node within a combinational circuit to SET propagation. The tool includes a fully analytical SET propagation model developed previously and considers both electrical and logic masking. After an initial path pruning phase based on logical analysis to determine true paths, the tool computes the minimum width and minimum height...
The continuous devices shrinking has introduced new challenges to integrated circuit design, mainly to deal with the overall yield loss [1]. Designers start to take into account process variability impact in the early design stages to successful deal with yield loss. Process variability have a critical effect on integrated circuits increasing power consumption to out of design specifications, accelerating...
Nowadays a number of energy simulation tools are available for analyzing the probable energy implications and related impacts of the proposed building project. These tools work on the information about the various aspects of proposed building - either input by the user or imported from CAD tools. Extraction of building data directly from the 2D CAD tools is still in preliminary stages and is part...
Process parameter variability in IC manufacturing has become an increasingly important issue as feature scaling descends further into the deep submicron region. Within industry the development of EDA tools associated with “process-aware-design” has a high priority as the impact on circuit performance due to process variations is having increasingly adverse effects on yield and performance. VARMA is...
The design of a Multiprocessor System-on-Chip (MPSoC) is a complex task, including steps as application development, platform configuration, code generation, task mapping onto the platform and debugging. An integrated environment covering most of these steps is a gap in the literature. The present work first details an MPSoC architecture, which supports the execution of distributed applications, including...
Since singular point extraction plays an important role in many fingerprint recognition systems, a digital circuit to implement such processing is presented herein. A novel algorithm that combines hardware efficiency with precision in the extraction of the points has been developed. The circuit architecture contains three main building blocks to carry out the three main stages of the algorithm: extraction...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.