The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In WSN, to ensure the lifetime durability of node, designers must take into account the constraint of energy consumption when specifying and designing an application. In this paper, a simulation tool for WSN is presented. The network model considered here is composed of the communication channel and node models which are both described with a function approach. The main goal of this work is to highlight...
Chirp-sequence-based Frequency Modulation Continuous Wave (FMCW) radar is effective at detecting range and velocity of a target. However, the target detection algorithm is based on two-dimensional Fast Fourier Transform, which uses a great deal of data over several PRIs (Pulse Repetition Intervals). In particular, if the multiple-receive channel is employed to estimate the angle position of a target;...
In recent years, research in IoT-enabled smart building solutions has accelerated significantly, thanks to the coming of age of wireless distributed sensing hardware, protocols and software. Moreover the computational capability of mobile and wireless platforms is now significant and complex tasks can be distributed and executed over remote low-power nodes. Data can be processed locally on-board to...
This paper presents the design of a prototype for a wearable device that implements a recognition system based on in-air signature into a FPGA that receives data from a 3-axis accelerometer. The Dynamic Time Warping (DTW) algorithm has been analyzed and simplified to reduce the complexity of the hardware architecture that implements the matching in the FPGA. Despite simplification, accuracy of the...
Nowadays, one of the main limiting factor in multiprocessor development is the increasing speed gap between efficient processing elements and slow main memories. To reduce this limitation, prefetching mechanisms, implemented in memory hierarchy, attempt to predict the future data needed in local memory. However, classical proposed solutions are no longer efficient for typical access sequences in the...
Technology scaling enables today the design of ultra-low cost wireless body sensor networks for wearable biomedical monitors. The typical behaviour of such systems consists of multi-channel input biosignals acquisition data compression and final output transmission or storage. To achieve minimal energy operation and extend battery life several aspects must be considered ranging from signal processing...
This paper presents the Parallel Heterogeneous Architecture Technology (PHAT), a scalable design methodology for prototyping and evaluating heterogeneous arrays of software-programmable VLIW processors and both manually designed and automatically-compiled custom hardware accelerators, using a shared memory architecture for communication. We discuss the trade-offs and breakeven point for switching...
We present a framework for fast prototyping of embedded video applications. Starting with a high-level executable specification written in OpenCV, we apply semi-automatic refinements of the specification at various levels (TLM and RTL), the lowest of which is a system-on-chip prototype in FPGA. The refinement leverages the structure of image processing applications to map high-level representations...
Parallelizing software is a popular way of achieving high energy efficiency since parallel applications can be mapped on many cores and the clock frequency can be lowered. Perfect parallelism is, however, not often reached and different program phases usually contain different levels of parallelism due to data dependencies. Applications have currently no means of expressing the level of parallelism,...
Matrix inversion is a computationally intensive basic block of many digital signal processing algorithms. To decrease the cost of their implementations, programmers often prefer the fixed-point arithmetic. This arithmetic requires less resources and runs faster than the floating-point arithmetic, but all the arithmetical details must be handled by the programmer. In this article, we overcome this...
This paper presents the application and evaluation of high-level synthesis (HLS) tools for a complex video processing algorithm. As case study predictive block-based motion estimation is chosen. The hardware implementation of the algorithm is introduced, and the implementation using HLS tools is presented, including various tips and pitfalls. The resulting HLS generated code is compared to a hand-coded...
Data compression is the process of representing information in a compact form, in order to reduce the storage requirements and, hence, communication bandwidth. It has been one of the critical enabling technologies for the ongoing digital multimedia revolution for decades. In the variable-length encoding (VLE) compression method, most frequently occurring symbols are replaced by codes with shorter...
This paper proposes and validates a new methodology to facilitate the analysis of modern data-intensive applications. A major part of handling the processing needs of these applications consists in using the appropriate Model-of-Computation (MoC) which guarantees accurate performance estimations. Our methodology introduces one major contribution that facilitates the analysis step in the co-design...
The software productivity gap tends to increase with both hardware and software complexities. At the same time, new semiconductor technologies will come with an increase of the cost. This long term trend justifies the emergence of new tools to simplify the design process of embedded systems and to optimize the use of available resources in terms of execution time and power consumption. The session...
Connection-oriented Guaranteed-Throughput (GT) mesh-based Networks on Chip (NoCs) have been proposed as a replacement for buses in real-time stream processing systems but are currently rarely used as hardware cost tends to be higher than conventional interconnects. Recently an interconnect with a ring topology was introduced as a low-cost alternative for use in medium scale homogeneous Multiple Processor...
Mapping a dataflow application onto a heterogeneous multiprocessor platform cannot longer be static. It has to adapt dynamically depending on the data and on the communication between the computation cores. This is typically the case for mobile devices that run multimedia applications. This paper presents an algorithm fast enough to be executed at run-time. In addition to computation cost, our approach...
This demonstration paper presents a multicore Real Time Operating System (RTOS) that schedules a parameterized dataflow Model of Computation (MoC) onto a multicore Digital Signal Processor (DSP) at runtime. This RTOS called Synchronous Parameterized and Interfaced Dataflow Embedded Runtime (SPIDER) exploits the Parameterized and Interfaced Synchronous Dataflow (PiSDF) MoC and its features at runtime...
Blood vessel detection from high resolution fundus images is a necessary step in several medical applications. Automatic blood vessels detection is a computing intensive task which raises the need for accelerated hardware architectures. In this paper, we propose a scalable hardware architecture for blood vessel detection using a matched filter (MF). The algorithm is made hardware friendly using parallel...
Although the research on the design of heterogeneous concurrent systems has a long and rich history, a unified design methodology and tool support have not emerged so far. Therefore, the creation of such systems remains a difficult, time-consuming and error-prone process. The absence of principled support for system evaluation and optimization at high level of abstraction makes the quality of the...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.