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We propose a two-pronged approach to reducing the impact of thermal cross-talk between components of disparate thermal operating points within a heterogeneously integrated electronic package. First, a low thermal conductivity interposer enhanced with an array of conductive thermal vias is employed to provide a high degree of lateral thermal isolation while providing adequate conduction in the vertical...
In this paper, an ultra low power CMOS-only voltage reference is presented. The reference exploits the work function difference between anti-doped (flipped-gate) and standard-doped nMOS devices. These devices require no additional processing and are realizable from the basic N+ and P+ implants used to implement the standard enhancement mode MOS devices on the process. The reference is implemented...
Low-resistance lateral pin junctions for LDs on III-V CMOS photonics platform are obtained using Si implantation and Zn diffusion owing to high thermal tolerance of III-V-OI wafer, resulting in observing electro-luminescence from Inga Asp photonic-wire waveguides.
In utilizing CMOS-MEMS resonators as mass-sensitive platforms, a uniform temperature distribution on the membrane surface is critical. In this paper, a novel design of CMOS-MEMS resonator with embedded microheater to control the temperature over the sensing layer was successfully designed and characterized. The CMOS-MEMS resonator was fabricated using 0.35 µm CMOS and post-CMOS micromachining process...
For advance CMOS device manufacturing, HALO implant with high tilt angles (30–45°) and 4-rotational condition has become one of the critical implant steps defining device properties. However, from Ion Implanter tool hardware point of view, the rotation mechanism function is not able to be monitored or verified to be accurate. A failure to rotate will not generate any tool error on traditional implanter...
This paper demonstrates a novel magnetic induced injection method of ferromagnetic composite to build electrically conductive through-silicon vias (TSVs). The through conductive via is filled with conductive ferromagnetic composite by attractive magnetic force. The composite is made of the mixture of silver and iron nanoparticles. SU-8 2002 is covered on the side walls of via as an insulating material...
In an integrated circuit, a resistor can be achieved in silicon technology by using poly silicon of diffusion areas but a resistor of practical value based on this technique suffers the limitation of resistance value and also its resistance value can not variable. Moreover, only a positive resistor can be achieved from silicon technology. This paper presents a new tunable floating resistor using operational...
This study focuses on the prototype of a 3D circuit in 65nm CMOS node, in which digital and analog functions have been partitioned on two different layers, assembled in a face-to-face integration and reported on a BGA. The paper more specifically presents the process technology carried out for the realization of the bottom die. Major process steps are described and evaluated from an electrical performance...
The use of high mobility channel materials such as Germanium can increase the pMOSFET drive current, thus improving the switching speed of CMOS. In this study the impact of the lateral spacer thickness on the performance of a 20 nm gate-length implant-free quantum well (IFQW) Ge pMOSFET is investigated using comprehensive full-band Monte Carlo simulations. The results of these simulations show that...
In this paper, the authors demonstrate a method to produce nanostructures and nanowires with dimensions down to 10nm by a self-alignment process using the standard CMOS spacer technology. In this process, very accurate alignment is achieved because the alignment is not determined by the lithographic tool but by the structures and materials themselves. The spacer technique is commonly used in the fabrication...
This paper proposes a 3D stacked buck converter with a 15μm thick spiral inductor on a silicon Interposer, which is suitable for fine-grain power-supply voltage control in SiP's. Our newly developed silicon interposer technology realizes a fine-pitch design rule (Line/Space=20μm/20μm, via hole diameter =30um) at the metal thickness of 15μm as well as conventional interposers with 5μm metal thickness...
Northrop Grumman Aerospace Systems (NGAS) is developing an Advanced Heterogeneous Integration (AHI) process to integrate III-V semiconductor chiplets on CMOS wafers under the Compound Semiconductor Materials on Silicon (COSMOS) DARPA program. The objective of the program is to have a heterogeneous interconnect pitch and length less than 5 um to enable intimate transistor scale integration. This integration...
The present paper aims at integrating thin films as passive components in the Back End of Line of an industrial Si-based CMOS technology while keeping limited additional technological steps. TiNxOy and TixTayO thin films deposited by magnetron sputtering were respectively investigated as resistive and high-k materials dedicated to highly integrated resistors and capacitors. We report here on electrical...
MOS-Triggered Silicon Controlled Rectifier(SCR) has been used as on chip Electrostatic Discharge (ESD) protection. However, the inherit slow turn-on speed is a major drawback of SCR. The compact MOS-Triggered SCR devices have been proposed and investigated in a 0.13μm CMOS process with the consideration of turn-on speed. From the test results, the turn on time of compact MOS-Triggered SCR has improved...
In this paper, we present a cost-effective JFET integrated in 0.18μm RFCMOS process. The design is highly compatible with standard CMOS process, therefore can be easily scaled and implemented in advanced technology nodes. The design impact on Ron and Voff is further discussed, providing the insights and guidelines for JFET optimization. Besides the superior flicker noise (1/f noise) characteristics,...
This paper explores the challenges facing the 22nm process generation and beyond. CMOS transistor architectures such as ultra-thin body, FinFET, and nanowire will be compared and contrasted. Mobility enhancements such as channel stress, alternative orientations, and exotic materials will be explored. Resistance challenges will be reviewed in relation to key process techniques such as silicidation,...
Incorporation of platinum (Pt) into nickel silicide (NiSi) improves the reliability and thermal stability of electrodes in Si MOSFETs. Increasing the Pt content is desirable for further scaled CMOS, but incorporation of more Pt would tremendously increase the material cost. In addition, since Pt is one of the key materials for eco-technology such as catalyst for exhaust absorption and so on, reduction...
Ge/Si core/shell gate-all-round nanowire pMOSFET integrated with HfO2/TaN gate stack is demonstrated using fully CMOS compatible process. Devices with 100 nm gate length achieved high ION of ~946 ??A/??m at VG - VT = -0.7 V and VDS = -1 V and on/off ratio of 104 with decent subthreshold behavior. Significant improvement in hole mobility and ballistic efficiency is demonstrated as a result of core/shell...
High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7-μm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded for the first time. The impact of ultra thin wafer on strained transistors and Cu/low-k multilevel interconnects is described. Properties examined include Kelvin and stack chain resistances of Cu interconnects as well as Ion-Ioff,...
Three dimensional silicon integration technologies are gaining considerable attention as the traditional CMOS scaling becoming more challenging and less beneficial. The advanced packaging solutions based on thin silicon carrier are being developed to interconnect integrated circuits and other devices at high densities. A key enabling technology element of the silicon carrier is through silicon via...
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