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Ion Implantation and Anneal processes are very important for Transistor Characteristics. Even scaling devices such as 3D structures require junction engineering involving implantation and anneal processes to boost device performance. This paper will discuss some key issues in the DRAM cell and peripheral transistor, and propose requirements of processes and hardware. Data were evaluated in Logic and...
Application of process and device TCAD is used for design and optimization of process integration of fully complementary Vertical PNP (VPNP) transistor into a Bi(CMOS) technology [1]. The paper addresses two selected tasks — optimization of vertical isolation and process integration of P-collector for the VPNP.
We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground...
PLAD (plasma doping) is promising for both evolutionary and revolutionary doping options because of its unique advantages which can overcome or minimize many of the issues of the beam-line (BL) based implants. In this talk, we present developments of PLAD on both planar and 3D device structures. Comparing with the conventional BL implants, PLAD shows not only a significant production enhancement,...
The conventional open gate ISFET sensor is normally very sensitive to light exposure which influences the sensor characteristics. In this study, different process conditions of ISFET were simulated using SILVACO TCAD in order to find the right doping profile which minimizes light effect. Various channels doping levels for ISFET sensor have been analyzed. Comparison with SRP samples was done in order...
This paper presents a simple but effective way to improve an NMOS transistor's ESD robustness for use in I/O pads. Simulation and physical failure analysis has been performed to identify the source of the ESD failure. Process splits have been performed primarily at LDD (Lightly Doped Drain) implant and salicidation process based on data presented in this paper. Both TLP (Transmission Line Pulse) measurements...
This paper for the first time reports on a novel “local” charge balanced trench-based super junction transistor. The local charge balance is achieved by selectively growing thin highly-doped n-type and p-type layers in a deep trench structure. The final charge-balanced trench structure is finished with an oxide-sealed airgap. Devices rated at 10A with Vbd=730V and a Ron=23 mΩ.cm2 are demonstrated.
We experimentally demonstrate a super-junction LDMOS transistor in a 0.18 mum BCD technology. The buffered super-junction structure is implemented by the use of existing N- and P-drift layer, which are optimized for conventional 20 V to 30 V LDMOS transistors. The breakdown voltage and the specific on-resistance of the fabricated super-junction LDMOS are 98.6 V and 1.01 mOmegaldrcm2, respectively...
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