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This paper reports on the technology and design aspects of an industrial DHEMT process for 650V rated GaN-on-Si power devices, using an in-situ MOCVD grown SiN as surface passivation and gate dielectric, with low interface state density and excellent TDDB. Optimization of the GaN epi stack results in very low off-state leakage (<10nA/mm). Due to the reduction of buffer trapping, low dynamic Ron...
This paper reports on an industrial DHEMT process for 650V rated GaN-on-Si power devices. The MISHEMT transistors use an in-situ MOCVD grown SiN as surface passivation and gate dielectric. Excellent off-state leakage, on-state conduction and low device capacitance and dynamic Ron is obtained. Initial assessment of the intrinsic reliability data on the in-situ SiN is provided.
A wafer scale investigation of AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) fabricated with a 4in. Si CMOS compatible technology is presented in this paper. High performance AlGaN/GaN MIS gated HEMT (MIS-HEMT) and passivated HEMT (i-HEMT) were fabricated using thin HfO 2 and CVD Si 3 N 4 as the gate and passivation insulator, respectively. Gate and drain leakage...
Innovative 800V/300°C AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) fabricated with a 4-inch Si CMOS compatible technology are presented in this paper. High performance AlGaN/GaN MIS gated HEMT (MIS-HEMT) and passivated HEMT (i-HEMT) were fabricated using 5nm-thick HfO2, and 30nm-thick CVD Si3N4 as the gate and passivation insulator, respectively. Contact resistance maps yield reduced...
This paper for the first time reports on a novel “local” charge balanced trench-based super junction transistor. The local charge balance is achieved by selectively growing thin highly-doped n-type and p-type layers in a deep trench structure. The final charge-balanced trench structure is finished with an oxide-sealed airgap. Devices rated at 10A with Vbd=730V and a Ron=23 mΩ.cm2 are demonstrated.
Large threshold voltage shifts are observed in n-type integrated VDMOS transistors upon hot carrier stress. The effect is enhanced by the total internal temperature (ambient temperature + temperature increase due to power dissipation) of the device as well as by the gate oxide electric field. A model is presented and is used to extract the safe operating area (SOA) of the transistors. This is especially...
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