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An ultra-compact sub-1V CMOS bandgap reference circuit is presented. To reduce the chip area the proposed bandgap is realized with 40 stage stack-gate, which adopts a novel layout floorplan without any area penalty. This paper describes two bandgap circuits and are both fabricated in TSMC 16nm FinFET process. The first bandgap aims at applications requiring small-area (area 0.0023 mm2) that achieves...
This work presents the modeling of the impact of elevated temperatures on the SET occurrence and their characteristics in an IBM 65-nm Bulk CMOS technology. The calculations are performed by the combined MUSCA SEP3 platform and Cadence simulations. Comparisons between predictions and experimental data of the impact of temperature on the SET cross section(s) and the SET pulse-width are consistent....
The design of mixed-signal ASICs for space requires a detailed knowledge of the behaviour of the technology to be used in an environment imposing radiation levels and temperatures beyond those found in standard applications. Commercial foundries providing standard CMOS technologies do not usually have or make available data on the behaviour of their devices under those conditions. Instituto de Microelectrónica...
The requirements of segmented current-steering DAC's MSB part for transistor matching are very high. In this paper, a diagonal layout is presented which can meet very well the requirements of 12-bit DAC monotonicity. The DAC was developed in TSMC 0.18um process technology. As a result of measurements, the static errors are: DNL=±0.15LSB, and INL=±0.2LSB.
TID and displacement damage effects are studied for vertical and lateral power MOSFETs in five different technologies in view of the development of radiation-tolerant fully integrated DC-DC converters. Investigation is pushed to the very high level of radiation expected for an upgrade to the LHC experiments. TID induces threshold voltage shifts and, in n-channel transistors, source-drain leakage currents...
The impact of process local variation on FPGA configuration memory is studied in this paper. Memory cell stability is examined by simulations and experiments on 65 nm and 45 nm processes. A statistical simulation method, which correlates closely with product silicon, has been developed. The results show that the trend of process local variation and memory density scaling adversely impact FPGA configuration...
This paper presents a new CMOS amplifier with high common-mode rejection ratio (CMRR) and low offset, dedicated to integrated sensors, using total continuous-time design technique but without the need of trimming. This is based on cascading two high-gain differential stages to form a composite front-end gain stage for enhancing CMRR as well as reducing systematic errors, and incorporating an averaging...
Polarities of plasma charging damage in n- and p-channel MOSFETs with Hf-based high-k gate stack (HfAlOx/SiO2) were studied for two different plasma sources (Ar-and Cl-based gas mixtures), and found to depend on plasma conditions, in contrast to those with conventional SiO2. For Ar-plasma, which was confirmed to induce a larger charging damage, both n- and p-ch MOSFETs with high-k gate stacks suffer...
As mainstream processing technology advances into 65 nm and beyond, many factors that were previously considered secondary or insignificant, can now have an impact on chip timing. One of these factor is inversed temperature dependence (ITD). As supply voltage continues scaling into sub-IV territory, delay-temperature relationship can be reversed on some cells, meaning that device switching time may...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
A 53 dB gain limiting amplifier for OC-192 and 10 GbE applications is developed in a 50 GHz fT SiGe SOI complimentary bipolar process, and has 5 mV pk-pk sensitivity, 1.25 V pk-pk maximum input signal, 14 ps (20/80%) rise/fall times and 450 mV pk-pk output into matched differential 50 Ohm loads, consuming 430 mW on a 3.3 V supply. Input Cherry-Hooper gain stages limit the -3 dB bandwidth to 11 GHz...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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