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This paper proposes a comparison of the two most advanced algorithms for connected components labeling, highlighting how they perform on a soft core SoC architecture based on FPGA. In particular we test our block based connected components labeling algorithm, optimized with decision tables and decision trees. The embedded system is composed of the CMOS image sensor, FPGA, DDR SDRAM, USB controller...
Nowadays, embedded vision systems have to face new hard requirements involved by modern applications: real-time processing of high resolution images issued by multiple image sensors. Recently, a new adaptable ring-based interconnection network on chip has been proposed. Based on adaptive datapath, it allows handling of multiple parallel pixel streams. In this paper, we present a new hierarchical memory...
Recognizing a specific moving target and capturing image with its trajectory has a wide range of applications. This paper introduces an embedded network video device system scheme which is used for target tracking and it is based on FPAG, ARM and Embedded Linux OS. The embedded network device consists of three main parts: image acquisition, image transmission, image processing included image recognition...
In this paper we present a class of emergent algorithms called Marching Pixels which can be used for real time image processing in smart camera chips. Marching Pixels are based on hardware agents which are virtually crawling in a pixel grid image to find attributes like centroid, rotation and size of an arbitrary number of objects given in an image. Due to the distributed and local processing scheme...
A single-chip FPGA implementation of a vision core is an efficient way to design fast and compact embedded vision systems from the PCB design level. The scope of the research is to design a novel FPGA-based parallel architecture for embedded vision entirely with on-chip FPGA resources. We designed it by utilizing block-RAMs and IO interfaces on the FPGA. As a result, the system is compact, fast and...
This paper presents a hardware architecture for calculating the city-block and chessboard distance transform on binary images. It is based on applying multiple morphological erosions and adding the result, enabling both processing pixels in raster scan order and a deterministic execution time. Which distance metric to be calculated is determined by the shape of the structuring element, i.e. diamonds...
A simple image-processing application is implemented on the Ambric MPPA and an FPGA, using a similar implementation for both devices. FPGAs perform extremely well on this kind of application and provide a good benchmark for comparison. The Ambric implementation starts out with a naive implementation and proceeds through several design optimizations until it reaches a maximum frame rate of 164 FPS...
Bilinear interpolation is widely used in computer vision for extracting pixel values for positions that lie off the pixel grid in an image. For each sub-pixel, the values of four neighbors are used to compute the interpolated value. This presents a challenge since four pixels must be read from the source image memory for each output pixel. This paper presents an architecture, for implementation within...
Smart camera system design and implementation is a challenging task due to the constant need to perform computationally demanding image processing tasks with the limited resource constraints of embedded systems. This paper presents the hardware and software co-design and implementation of the first stage of TraffiCam, an FPGA based smart camera prototype for traffic surveillance at intersections,...
This paper describes the idea of the multi-core programmable cores architecture for real-time image processing in embedded applications. The authors propose the architecture of a simple 8-bit processor core dedicated to low and intermediate level image operations. Several cores are connected to a common, 128-bit wide data bus by multiplexes and their operation is synchronized. The image data on the...
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