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A wide-locking range divide-by-4 static frequency divider for the mm-wave wireless applications is proposed. The capacitive-bridged inductive shunt peaking technique is investigated for widening the locking range and a compact layout area. The divider is realized in 65nm LP CMOS with a small area of 100μm × 160μm occupied. Measurement results show the present divider achieves an operation range percentage...
This article presents the design and implementation of a multi-stage radio-frequency (RF) passive polyphase filter (PPF). The layout parasitics and mismatch which deteriorate significantly the RF filter performance are analyzed and modeled. To reduce this parasitic degradation, a novel optimal layout technique is proposed. It is based on reproducing the same optimized PPF stage layout for the different...
This paper presents a compact wideband amplifier at 160 GHz in 40-nm CMOS. Typical wideband amplifier design requires higher-order matching networks and more gain stages, both of which demand larger die area. The presented 8-stage amplifier uses a compact “fishbone” layout technique, and its core size is as small as 190 × 123 µm2. A small-signal gain of 15 dB at 160 GHz and a 3-dB bandwidth of 41...
A 6.336–6.864GHz power amplifier for band 7 of ultra-wideband(UWB) is presented in this paper, which consists of a differential cascode output stage and a gain-tuning stage by changing bias voltage. Implemented in 0.13-µm CMOS technology, the power amplifier has a gain range of −14–1dB, output 1-dB compression point of +1dBm and output third order intercept point(OIP3) of +11dBm. Simulation results...
Users of test equipment such as oscilloscopes expect performance and accuracy beyond the level of their device under test in order to insure measurement results correspond to the DUT, not to limitations of the test equipment. This drives the use of bipolar circuitry at the front-end of high-bandwidth oscilloscopes, even if targeted at testing devices in a marketplace dominated by CMOS. Several circuit...
Design information is given for developing microwave and millimeter-wave silicon based low noise broadband monolithic transimpedance amplifiers. The required layout optimizations for SiGe HBTs and CMOS devices are described and the foundry selection criteria we employed are reported. An efficient high frequency passive devices implementation and high frequency connectivity solutions with external...
The impact of layout on the responsivity and bandwidth of photodiodes is studied and summarized. The photodiodes are fabricated in a 0.18µm CMOS SOI process technology. The measurements are performed at wavelengths near 850nm.
In this paper we present a 2GSps 12bit current steering digital-to-analog converter (DAC), in 100G Ft 0.18µm SiGe HBT technology. An improved switching sequence is proposed to compensate the gradient error and reduce the impact of cell-dependent-delay-variation. According to measured results, the test chip achieved a DNL/INL of 0.6/0.95 LSB respectively. The measured SFDR at low frequency is above...
This paper describes total ionizing dose and single event effects data for CMOS operational amplifiers implemented using RadHard-By-Design (RHBD) design and layout techniques. i.e., edgeless nMOSFETs, fully isolating guard rings, and robust circuit topology. This work is part of Aeroflex's larger effort to provide a complete family of radiation hardened analog function components.
This paper describes the design of a 10 Gb/s Laser Diode Voltage Driver (LDVD) circuit using 0.18 um CMOS technology. The LDVD circuit consists of input buffer stage, preamplifier stage and output driver stage. The LDVD uses dual power supplies, including the 1.8 V supply in the pre-amplifier stage and the 3.5 V supply in the output driver stage. In order to increase the bandwidth, the pre-amplifier...
A folding technique is proposed to reduce the size of CPW based branch-line couplers without compromising their electrical characteristics. The technique is used to fabricate a high-performance 90° 70–80 GHz hybrid coupler in 130-nm CMOS with a 35% layout area reduction. Grounded coplanar waveguide (CPWG) based structures are used for the low impedance lines while complying with the CMOS metal spacing...
A passive low-pass filter on CMOS 130nm process is presented in this paper. The filter has an elliptic transfer function to give the sharpest out of band rejection with the lowest order. The bandwidth of the filter is from DC to 6GHz which makes it applicable to wide band zero IF receiver architectures. The filter has a balanced implementation in order to be integrated with a balanced mixer and shows...
A limiting amplifier for STM-1 systems of SDH optical communication in 0.35μm CMOS technology under 3.3V/5V supply voltage is presented. It adopts four cascaded differential amplifiers in a mixed structure of differential pairs and source followers which effectively expands the bandwidth. A DC offset compensation circuit is designed to compensate the mismatch caused by process manufacture and layout...
Folded Cascode OTA is widely used in analog and mixed signal domain. It gains special importance in switched capacitor circuits where folded cascode architecture is the default choice for op-amps. In this work, a digitally programmable single ended folded cascode operational transconductance amplifier (OTA) is presented. Observations show that the OTA can be made digitally programmable over a wide...
A pseudo segmented twofold time-interleaved 6-bit digital-to-analog converter (DAC) occupies 0.28 mm2 chip area in a standard 90 nm CMOS technology. The DAC enables sampling rates up to 28 GS/s with a power consumption of 2.25 W at a −2.5 V power supply. The output bandwidth is at least 14 GHz. The integral non-linearity (INL) and the differential non-linearity (DNL) are 0.8 LSB and 1 LSB respectively...
In this paper, a Q-band common source low noise amplifier (LNA) using 90-nm standard RF-CMOS technology is proposed. The design methodologies for millimeter-wave (MMW) amplifiers are discussed. The post layout simulation results show that S11 is lower than -14 dB and S22 is -11 dB at the peak gain of 14.6 dB at 37.5 GHz with 9.4 GHz bandwidth, the minimum noise figure is lower than 5.5 dB, the input...
In this report, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with current-mode single-ended amplifier, this OTA reduce parasitic taking by gain-boost amplifier to achieve high-gain and high-speed. Besides, a dual phase SC-CMFB circuit is introduced, and some methods are concerned to improve the performance. Then, by optimization the layout design,...
This paper presents a design of a 3rd order Butterworth Gm-C Low Pass Filter (LPF) for WiMAX receivers in a 90 nm CMOS process. Due to its robustness to process parameter tolerances, a passive LC-ladder filter was emulated using the Signal Flow Graph (SFG) method. As a building block for the LPF, a highly linear operational transconductance amplifier (OTA) based on bias-offset cross-coupled differential...
An 8 Tb/s 1 pJ/b 0.8 mm2/Tb/s inductive-coupling interface between 65 nm CMOS GPU and 0.1 ??m DRAM is developed. BER <10-16 operation is examined in 1024-bit parallel links. Compared to the latest wired 40 nm DRAM interface, the bandwidth is increased 32??, and the energy consumption and layout area are reduced by 8?? and 22??, respectively.
A Variable Gain and Attenuation control Amplifier (VGA) operating with low power, wide bandwidth and large Gain range for interfacing 60GHz RF front-end to Digital Baseband processor has been designed in 180nm SiGe BiCMOS technology from Jazz Semiconductor. The VGA is implemented using two stage amplifier followed by a Buffer stage with additional Diode linearizer for improving the input referred...
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