The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Gate semi-around silicon nanowire (SiNW) FETs have been fabricated and their electrical characteristics, especially on the drivability, have been assessed for future high performance devices. Among different wire size, a SiNW FET with a cross-section of 12 × 19 nm2 has shown an improvement in the on-current (ION) when normalized by the channel peripheral length. A high ION over 1600 μA/μm at an overdrive...
We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET IDSAT = 825/950 μA/μm (circumference-normalized) or 2592/2985 μA/μm (diameter-normalized) at supply voltage VDD = 1 V and off-current IOFF = 15 nA/μm. Superior NW uniformity is obtained...
A new universal stress retardation parameter set is successful to account for initial oxidation rate enhancement, orientation-dependent retardation and self-limiting phenomena observed in the dry oxidation experiment of the silicon FIN nanostructures over a wide temperature range. This stress-retarded orientation-dependent model was proved to be trustworthy in shape engineering of silicon nanowire...
The oxidation of electrochemically etched porous silicon (PSi) has demonstrated success in the formation of device quality localized SOI for CMOS applications. A primary advantage with a localized SOI formation is the ability to integrate novel device structures and optoelectronics (i.e. optical switches, waveguides) with bulk silicon CMOS. The formation of PSi can be done selectively by controlling...
We demonstrate a bulk silicon alternative to the conventional silicon-on-insulator photonics platform. We show waveguide losses of 10 dB/cm with a technique that can be implemented on the front-end of a typical CMOS fabrication line.
Although the strained-Si channel engineering seems to be rather compatible with the existing mainstream CMOS process, the use of strained Si on SOI virtual substrates introduces new process and integration issues that need to be addressed for successful manufacturability and reliability. Even for ideal strained Si on SOI substrates, the impacts of various CMOS process steps, e.g., patterning, oxidation,...
Atomically flat silicon surface constructed with atomic terraces and steps is realized by pure argon ambience annealing at 1200degC on (100) crystal orientation large diameter wafers with precisely controlled tilt angle. Only the radical reaction based insulator formation technology such as oxidation utilizing oxygen radicals carried out at low temperature (400degC) can preserve the atomically flatness...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
In this paper, we demonstrate CMOS characteristics on a Si(110) surface using surface flattening processes and radical oxidation. A Si(110) surface is easily roughened by OH- ions in the cleaning solution compared with a Si(100) surface. A flat Si(110) surface is realized by the combination of flattening processes, which include a high-temperature wet oxidation, a radical oxidation, and a five-step...
As device dimensions have reduced to nanometer length scales, rapid thermal processing (RTP) has emerged as the key approach for providing the low thermal budget and ultra-pure process conditions that are essential in advanced fabrication schemes. As further progress in electronic technology becomes increasingly dependent on success in rapid development cycles that include both materials innovations...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.