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In this paper, we analyze, for the first time to our best knowledge, the high-temperature perspectives of Ultra-thin body (UTB) SOI MOSFETs. High-temperature behavior of threshold voltage, subthreshold slope, transconductance maximum and on-current is analyzed in details through measurements and 2D simulations. Particular attention is paid to the effect of buried oxide (BOX) and Si film thicknesses...
The electrical performance of fully depleted double gate MOSFET devices with vertical structure feature were evaluated with the implementation of oblique rotating implantation (ORI) method for several silicon pillar thicknesses using virtual wafer tool. The difference in the subthreshold performance is well noticed, as well as the potentials across the channel for different geometries. The implication...
Lateral channel engineering utilizing halo-pocket implant surrounding drain and source regions is effective in suppressing short channel effects. However, the reported model cannot be extended further to the pocket implantation, where inhomogeneity along the channel is the main cause for the reverse short channel effect (RSCE). A strong reverse short channel effect suppresses the short channel effect...
The impact of strain on the threshold voltage of nanoscale strained-Si/SiGe MOSFETs is studied by developing a compact analytical model. Our model includes the effects of strain (Ge mole fraction in SiGe substrate), short-channel length, source/drain junction depths, substrate (body) doping, strained silicon thin-film thickness, gate work function, and other device parameters. The model correctly...
Continued challenge for higher-performance semiconductor device requires the controlled doping of single-dopant atom to control the electrical properties. Here we report the fabrication of semiconductors with both dopant number and position controlled by using a one-by-one doping technique, which we call "single-ion implantation" (SII). This technique enables us to implant dopant ions one-by-one...
The paper presents a study of threshold voltage for poly-silicon TFTs through a designated experiment with several split conditions on the LDD implantation. Our results show that the abnormality of threshold voltage is caused by the effect of poly grain boundary trapping combining with the LDD condition along the channel edge region. In addition, PLN process is found to be another factor for the threshold...
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