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Power Dissipation being an important parameter of any electronic system's performance is a major topic of interest for scads of researchers. Frequency divider, a basic building block in ample electronic systems, dissipates a very high power and consumes substantial amount of energy. In this paper a frequency divider-by-3 circuit is implemented using diode free adiabatic logic (DFAL), which surpasses...
A CMOS Track-and-Hold circuit which can accommodate 700 MHz to 1 GHz of input frequency with a sampling rate of 5 GS/s is presented. This T/H circuit acts as a sampling circuit in front end of high speed analog-to-digital converters that are applicable in television and radio signal transmissions. The T/H circuit, which includes transmission gate switches, hold capacitors and output buffers, is designed...
In recent years, VLSI designers are more concerned about power minimization of digital circuits and in this field the reversible logic design has emerged as one of the powerful tool due to its low power consumption feature. Adiabatic logic is also an attractive solution for energy minimization. In this paper, we have combined both the adiabatic and reversible logic. The basic reversible logic gates...
A low-power hybrid analog-to-digital converter (ADC) architecture for high-speed medium-resolution applications is introduced. The architecture is a subranging time-interleaved ADC. In the first stage, a fast flash ADC resolves the three most significant bits. The remaining bits are generated by four time-interleaved low-power successive approximation register (SAR) ADCs, leading to 8-bit 1GS/s operation...
A low-voltage fully differential current-mode continuous time delta-sigma modulator is presented for application in electrochemical sensor arrays. Although a first order topology is realized by using a single differential integrator, second order noise shaping is achieved. A differential quantizer based on current controlled oscillators (CCOs) allows a current-mode implementation with high noise-immunity...
Pixel detectors at HL-LHC experiments or other future experiments are facing new challenges, especially in terms of unprecedented levels of radiation and particle flux. This paper describes the progress made by the CHIPIX65 project of INFN for the development of a new generation readout ASIC using CMOS 65 nm technology.
Successive-approximation-register (SAR) analog-to-digital converters (ADCs) have generated a great deal of interest in the past several years. While most of the recent work focuses on low-to-moderate resolution designs (8 to 10b), we are now also seeing significant advancements in the high-resolution space, targeting ≥14b at 10 to 100MS/S [1,2]. Traditionally, this range has been dominated by pipelined...
At data rates beyond 10Gb/s, most wireline links employ NRZ signaling. Serial NRZ links as high as 56Gb/s and 60Gb/s have been reported [1]. Nevertheless, as the rate increases, the constraints imposed by the channel, package, and die become more severe and do not benefit from process scaling in the same fashion that circuit design does. Reflections from impedance discontinuities in the PCB and package...
To draw an accurate relationship between power dissipation and speed is a challenging problem in operational Amplifier with switch capacitance. However, transformation of current steer circuit into charge steer is an efficient technique to reduce power dissipation even at higher speed. In this paper, an efficient model is proposed to estimate the 1st and 2nd stage operational Amplifier's power dissipation...
Electrical biosensors are one strategy being explored for the development of a rapid point-of-care and onsite DNA testing tools since this technology is amenable to miniaturization, can be accurate and highly sensitive with simple instrumentation, and relatively inexpensive. A label free and fully integrated semiconductor sensor array based on differential charge-based capacitance measurement for...
Folding of analog signals is one of the most efficient techniques employed in digitization of high speed signals at intermediate resolution. However, its implementation is restricted by distortion resulting from limited bandwidth at the output of the folders, interpolation at the output and comparator offset. In this paper a method to increase input signal processing capabilities and reduce the number...
A high-accuracy CMOS interface for differential capacitive sensors using a time-to-digital converter (TDC) is presented for high-accuracy ratiometric operation. A capacitance-to-time converter (CTC) is developed based on a switched-capacitor (SC) sample/hold (S/H) circuit and an integrator. The proposed TDC achieves high resolution without using higher frequency clock signals. The Performances of...
We present a quadrature-generation method that is based on parametric energy transfer to an LC resonator. The phase-sensitive nature of parametric pumping is used to generate a signal in quadrature with an incoming clock signal. The pumped LC resonator is tuned by a digital calibration loop toward the input signal frequency across the tuning range. Phase interpolation is achieved by tuning the resonator...
A 12b two-step pipelined SAR ADC reports a 66.7dB SNDR and an 86.9dB SFDR for a 5MHz sinusoidal input at 160MS/s. A digital background calibration based on opportunistic PN injection treats both DAC mismatch and residue-amplifier gain errors. The calibration enables a significant downsizing of the ADC input capacitance to yield a wideband, highly linear input network and an over-80dB SFDR while digitizing...
Split-path data driven dynamic logic (SPD3L) is used wherever low power design is desired. It uses subset of input signals instead of global clock to maintain the correct pre-charge and evaluation phases. Elimination of clock network results in substantial reduction in power dissipation compared to dynamic domino logic. In this work, two 6×6 booth multipliers are implemented in 1.8V 0.18um CMOS technology,...
This paper presents a low-power true single-phase clock 2/3 prescalers at 1.2 V supply voltage. The true single-phase clock divider was developed to help achieve low power and highspeed. All simulation results have been carried out by using Hspice program simulator based on 0.13μm CMOS technology. The power consumption of the proposed circuit is less than that of the previous circuits. The prescaler...
With the increased interest in low power digital devices operating at low frequencies, the demand for high performance adiabatic logic circuits is on the rise. A frequency divider is extensively used for frequency synthesis in transceivers, and Phase Locked Loops (PLL) circuits. This paper proposes a novel diode free adiabatic logic (DFAL) based frequency divider for low power applications. The proposed...
A review of Time-to-Digital Converter (TDC) designs based on Cyclic Time Domain Successive Approximation interpolator method are presented in this paper. The new architecture of (TDC) aims at adjustable sub-ps-level resolution with high linearity in ms-level dynamic range. To achieve sub-ps-level resolution with cyclic time domain successive approximation (CTDSA) within a clock cycle, the propagation...
Dual threshold voltage (Vth) design is a common method for reducing leakage power in above-threshold circuits. This research shows that it is also effective in reducing energy per cycle of sub-threshold circuits. We first study the single-Vth design theoretically and by simulations, and find that the energy per cycle is independent of threshold voltage. However, in a dual-Vth design, the energy per...
A low-energy 8-bit 450-MS/s single-bit/cycle SAR ADC is presented. The design combines top-plate sampling, small unit capacitances (0.75 fF), symmetric DAC switching, and judicious delay optimization around a single high-speed comparator to achieve an ENOB of 7.6 at Nyquist, translating into an FOM of 76 fJ/conversion-step. The converter occupies an active area of 0.035 mm2 in 65-nm CMOS.
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