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This work focuses on generation of quadrature clocks with high phase accuracy and low noise, while reducing area and power consumption. The design objective is to make these quadrature oscillators suitable for applications in power- and area-constrained SOCs. We demonstrate in this work quadrature clock generation using parametric capacitance modulation in CMOS technology. We present a quadrature-generation...
We present a quadrature-generation method that is based on parametric energy transfer to an LC resonator. The phase-sensitive nature of parametric pumping is used to generate a signal in quadrature with an incoming clock signal. The pumped LC resonator is tuned by a digital calibration loop toward the input signal frequency across the tuning range. Phase interpolation is achieved by tuning the resonator...
Generating quadrature phases at low area and power overhead from a two-phase clock without frequency conversion is desirable for half-rate CDR architectures. This is useful for both embedded and forwarded clock systems, where quadrature generation by dividers, ring oscillators or coupled LC-VCOs is common. For example, [1] uses LC-VCOs followed by 2∶1 dividers to generate the half-rate clocks for...
We present a quadrature VCO based on mutual parametric pumping between two LC resonators. The design occupies 0.11mm2 in 65nm CMOS, consumes 16.8mW, and achieves a phase noise of −116.7dBc/Hz at 1MHz offset from a 6.57GHz carrier, while providing CMOS quadrature outputs. The measured phase error is less than 0.3° across the entire tuning range. Relative to state-of-the-art quadrature VCOs, it compares...
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