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The conversion time for high-speed analog-to-digital converters is limited by the rate at which the internal comparator(s) can amplify small voltages 1 into logic levels. Several comparators have been designed with response times of less than 10 ns [1,2]. However, these circuits are usually fabricated with bipolar transistors.
A high-speed low-power 1:16 demultiplexer with a novel symmetrical-edge-delay sense amplifier is presented in this paper. The traditional Sense-Amplifier-Based Flip-Flop (SAFF) has asymmetric rising and falling edges with the fact that the falling edge lags the rising edge the time of a gate delay, which has become a bottleneck of speed. In order to overcome the problem of nonsymmetry of output data...
Soft errors, radiation-induced transient faults latched by memory elements, have emerged to be one dominant failure mechanism for scaled CMOS designs. Therefore, this paper presents a robust design named soft error resilient latch (SERL). Compared to BISER, one of the latest latch designs, SERL demonstrates better soft error protection with smaller area overhead.
In high-speed serial communication interface circuits, a high-performance slicer is essential. This paper presents an improved slicer based on SA/FF (Sense Amplifier/Flip Flop) and extracts the sample function of whole circuit system. The results show that the proposed configuration can achieve a regeneration gain of 61.8dB and a −3dB bandwidth of 10GHz. The power consumption of the new structure...
A CMOS comparator using dynamic latch, suitable for high-speed Analog-to-Digital Converter (ADC) with high speed and low power dissipation is presented. The design is intended to be implemented in Sigma-delta ADC. This circuit combines the good features of the resistive dividing comparator and the differential current sensing comparator. The design has been carried out in Tanner EDA tools, the schematic...
The designing of high speed (ADC) analog to digital converter in low power for improving the performance like speed and power efficiency in dynamic latch comparator. This paper deals in reduction of leakage power and propagation delay of this dynamic latch comparator. Using various techniques designers can simulate and observe the different factors for enhancing the performance of the circuit. The...
This paper presents a resistor-free self-regulating CMOS ring oscillator (RO) whose oscillation frequency is insensitive to supply noise variations. The proposed RO design achieves self-regulation by adopting a cross-coupled dual latch-based scheme; Proper custom device sizing of the cross-coupled latches can improve supply noise immunity and frequency stability compared to a simple inverter design...
A 10-bit 50 MS/s current mode based SAR ADC is presented in this paper. The SAR ADC uses a Gm stage which converts the input voltage to a current which is then processed in a current based binary search algorithm SAR loop. In comparison to the conventional switched capacitor SAR ADC structures, the sampling capacitor size is smaller than the total capacitance of the comparable SC-SAR ADCs. Moreover,...
In todays scientific scenario the need for reducing power dissipation for high end devices like Analog to Digital Converters, operational amplifiers is of utmost importance. One of the important contributors to power dissipation is leakage current. In this paper we propose a charge sharing lector comparator which significantly reduces leakage current. The circuit is primarily based on the LECTOR technique...
In this paper we investigate the efficiency of using temporal and spatial hardening techniques in flip-flop design for single event upset (SEU) mitigation at different supply voltages. We present three novel SEU tolerant flip-flop topologies intended for low supply voltage operation. The most SEU tolerant flip-flop among the proposed flip-flop topologies shows ability of achieving maximum SEU cross-section...
In this paper we propose the novel Delta DICE latch that is tolerant to SNUs (Single Node Upsets) and DNUs (Double Node Upsets). The latch comprises three DICE cells in a delta interconnection topology, providing enough redundant nodes to guarantee resilience to conventional SNUs, as well as DNUs due to charge sharing. Simulation results demonstrated that in terms of power dissipation and propagation...
High speed analog to digital converters (ADC), memory sense amplifiers, RFID applications, data receivers with low power and area efficient designs has attracted a wide variety of dynamic comparators. This paper presents an improved design for a dynamic latch based comparator in achieving higher speed of conversion targeting 8-bit asynchronous successive approximation register (ASAR) ADC. The comparator...
This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with the tap...
This paper presents a 65nm CMOS 60Gb/s receiver frontend incorporating CTLE, FFE, DFE, output slicers and clock generation as well as distribution circuits. Current-integration along with cascode gain control is used to maintain equalizer linearity under varying gain without sacrificing power consumption. Interleaved deserializing slicers achieve the high gain required for adaptive error sampling...
This paper presents characterization of low operating voltage, high speed and power efficient comparator used as a basic building block in speed optimized Analog to Digital Converters (ADC), such as flash ADC. Overall performance of any ADC in terms of speed, resolution and power consumption highly depends on the underlying comparator being used. In this paper, better structure of comparator is implemented...
In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay. We also show a...
The building block in analog to digital converters (ADC) is comparator. To increase speed and power efficiency, low power comparators are required by the high speed ADCs. When the supply voltages are smaller, high speed comparators are more challenging to design. To compensate the design challenges, methods such as supply boosting techniques, techniques employing body-driven transistors, current-mode...
This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic...
This paper presents a 50Gbps half rate SerDes transmitter with automatic serializing time window search. By implementing a serializing time window search loop, the serializing timing is guaranteed and circuits running at highest speed such as latches for retiming and clock tree buffers for delay matching are eliminated. Fabricated in 65nm CMOS technology, the transmitter running at 50Gbps consumes...
This paper describes the implementation issues in designing a 1 tap current integrating half rate decision feedback equalizer. We introduce a new technique for designing an 8Gbps 1 tap half rate current integrating DFE in 40nm CMOS technology that draws 0.67mW from a 1.1V supply. The technique uses a delayed clock rather than speculation. This removes the speculation impact on power consumption and...
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