The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Power consumption and high compute density are the key factors to be considered when building a compute node for the upcoming Exascale revolution. Current architectural design and manufacturing technologies are not able to provide the requested level of density and power efficiency to realise an operational Exascale machine. A disruptive change in the hardware design and integration process is needed...
Recently, face recognition (FR) based on always-on CIS has been investigated for the next-generation UI/UX of wearable devices. A FR system, shown in Fig. 14.6.1, was developed as a life-cycle analyzer or a personal black box, constantly recording the people we meet, along with time and place information. In addition, FR with always-on capability can be used for user authentication for secure access...
Batteryless energy harvesting systems face a twofold challenge in converting incoming energy into forward progress. Not only must such systems contend with inherently weak and fluctuating power sources, but they have very limited temporal windows for capitalizing on transitory periods of above-average power. To maximize forward progress, such systems should aggressively consume energy when it is available,...
Programming heterogeneous multiprocessor architectures is a real challenge dealing with a huge design space. Computer-aided design and development tools try to circumvent this issue by simplifying instantiation mechanisms. However, energy consumption is not well supported in most of these tools due to the difficulty to obtain fast and accurate power estimation. To this aim, this paper proposes and...
With the development of multiple processors SoC (system on chip), there are more and more challenges to the design of NoC (network-on-chip), one of which is to design energy-efficient NoC architecture, due to its large power consumption. Multi-NoC (multiple network-on-chip) has been proposed to save leakage power for its advantages in power gating network components. In this paper, we propose a hybrid...
This article introduces an energy efficient heuristic that performs resource provisioning and Virtual Machine (VM) migration in the Disaggregated Server (DS) schema. The DS is a promising paradigm for future data centers where servers' components are disaggregated at the hardware unit levels and resources of similar type are combined in type respective pools, such as processing pools, memory pools...
High Efficiency Video Coding (HEVC) in-loop filtering includes the deblocking filter (DF) and the sample adaptive offset filter which consume about 20% of the total HEVC de coding time. In this paper a very energy efficient programmable multicore coprocessor for HEVC in-loop filtering is proposed. The coprosessor is placed and routed using leading edge 28nm technology to show that it can be clocked...
The requirements' demands of applications, such as real-time response, are pushing the wearable devices to leverage more power-efficient processors inside the SoC (System-on-chip). However, existing wearable devices are not well suited for such challenging applications due to poor performance, while the conventional powerful many-core architectures are not appropriate either due to the stringent power...
The traditional low-power embedded processors such as ARM and Atom are entering the high-performance server market. At the same time, big data analytics are emerging and dramatically changing the landscape of data center workloads. Thus, the question of whether low-power embedded architectures are suited to process big data applications efficiently, is becoming important. In this work, through methodical...
Modern SoCs are characterized by increasing power density and consequently increasing temperature, that directly impacts performances, reliability and cost of a device through its packaging. Thermal issues need to be predicted and mitigated as early as possible in the design flow, when the optimization opportunities are the highest. In this paper, we present an efficient framework for the design of...
Today's network architectures are not able to cope with the Future Internet requirements, as they are too inefficient, power hungry, and ossified on the TCP/IP paradigm. In order to promote a viable evolution towards new protocols and paradigms, modern network routers should become programmable to allow a flexible management of both traffic flows and power states. In this respect, Software Defined...
Our aim in the research is to address the scheduling problem of a uniform multiprocessor platform with a periodic task set. The processors in the platform have the same instruction architecture. Besides, each processor has a limited range of discrete available speeds and the speed of each processor can be adjusted independently from each other. We propose an off-line task-to-processor assignment algorithm,...
Among several optimizations provided by an optimizing compiler, it is a challenge, even for the most expert programmer, to know which compiler optimizations will generate the best target code. The goal of this paper is to describe a case-based reasoning approach that automatically selects a compiler optimization sequence that is able to outperform a well-engineered compiler optimization level in terms...
Throughput is a key performance metric for streaming FFT architectures. However, increasing spatial parallelism to improve throughput introduces complex routing, thus resulting in high power consumption. In this paper, we propose a high throughput energy efficient parallel FFT architecture based on Cooley-Tukey algorithm. Multiple pipeline FFT processors using time-multiplexing are utilized to perform...
Power consumption is crucial in embedded systems, mainly because of the limited battery capacity and the problem of heat dissipation. The energy efficiency of System-on-Chips (SoCs) is optimized at both hardware and software level using simulation platforms. The challenge of these platforms lies in the tradeoff between accuracy and simulation speed for early architecture exploration and HW/SW validation...
This paper proposed a 128-point FFT for low data rate Audio Visual PHY (AVPHY) mode of IEEE 802.15.3c standard. The architecture process a continuous flow of 2 samples in parallel, leading to a throughput of 317.25 MSamples/s with a symbol duration 492 ns. The FFT computed in seven stages that uses radix-2 butterflies and complex rotations. The radix-2 butterflies and complex rotations are time-interleaved...
The High-Performance Computing (HPC) community aimed for many years at increasing performance regardless to energy consumption. However, energy is limiting the scalability of next generation supercomputers. Current HPC systems already cost huge amounts of power, in the order of a few Mega Watts (MW). The future HPC systems intend to achieve 10 to 100 times more performance, but the accepted energy...
This paper introduces adaptive techniques targeted for heterogeneous manycore architectures and introduces the FlexTiles platform, which consists of general purpose processors with some dedicated accelerators. The different components are based on low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time. These features enable a breakthrough in term of computing...
Dynamic Voltage Frequency Scaling (DVFS) has been the tool of choice for balancing power and performance in high-performance computing (HPC). With the introduction of Intel's Sandy Bridge family of processors, researchers now have a far more attractive option: user-specified, dynamic, hardware-enforced processor power bounds. In this paper we provide a first look at this technology in the HPC environment...
Based on 32-bit reduced instruction set computing (RISC) CPU architecture, Andes's CPU series are called AndesCore which support designers to exploit SoC platform. Three major application classifications that N8, N9, N10 and N12 can be deployed to, are entry level MCU based application, mid range Linux or RTOS application, and high end Linux application, respectively. Each of N8, N9, N10 or N12, namely...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.