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Real-time embedded systems are present in various application domains such as automotive, aeronautical, space, and telecommunications. Avionics systems (i.e., aviation electronics) represent a specialized class for the aerospace branch. It is a fact that avionics are getting more and more complex considering functionality and design and also using an increased number of digital computer resources...
This paper proposes solution capable to process aerial images from UAVs to identify failures in plantations and makes a comparison of the system running on light sized computers and low power computing platforms. An algorithm was developed based on watersheds using OpenCV library. The solution was embedded on X86 architecture (AlteraDE2i-150) and Intel Edison boards as well as on ARM architecture...
Embedded systems are steadily growing in complexity and nowadays power consumption additionally plays an important role. Designing and exploring such systems embedded in its environment demand for holistic and efficient simulations. In this work we use a simulation framework based on the HLA (High-Level Architecture) and the modeling tool Ptolemy II to enable complex heterogeneous distributed simulations...
DIPLODOCUS is a UML profile targeting the design space exploration of Systems-on-Chip at a high level of abstraction. It is supported by an open source toolkit named TTool, which enables the designer to develop, simulate and formally verify SoC models. Up to now, performance criteria such as CPU and bus loads were the main metrics used for the exploration. The main objective of our research works...
The development of embedded systems is a complex and challenging task. Part of this complexity originates from limited resources and the need to solve tradeoffs between competing quality properties and goals. Producing a correct design therefore requires a complete and understandable requirements specification. Non-Functional Goals (NFGs) are commonly used to analyze these tradeoffs, while Model-Driven...
High contribution of cache access power in the total power consumption of embedded processors has made it a major concern in embedded system designs. By technology scaling, leakage power has created more stress on design constraint and power budget of embedded processors. Therefore; designers require a comprehensive design space exploration of cache architecture. In this paper we find out the optimum...
The amount of power that can be provided for charging the batteries of the electric vehicles connected to a single neighborhood step-down transformer is constrained by the infrastructure. This paper presents a distributed and collaborative residential-level power grid management application to alleviate the need of costly infrastructure upgrade. The application is designed to be hosted in our in-house...
One of the main challenges for embedded system designers is to find a tradeoff between performance and power consumption. In order to reach this goal, hardware accelerators have been used to offload specific tasks from the CPU, improving the global performance of the system and reducing its dynamic power consumption. Enabling the use of accelerators could become a tricky task for embedded system designers...
Mobile systems require high-performance and low-power SoC or 3D-IC chips to perform complex operations, ensure a small form-factor and ensure a long battery life time. A low supply voltage (VDD) is frequently utilized to suppress dynamic power consumption, standby current, and thermal effects in SoC and 3D-IC. Furthermore, lowering the VDD reduces the voltage stress of the devices and slows the aging...
This paper demonstrates the benefit of FPGAs for better power and energy efficiency when exploited for non-instruction fetch-based architecture. By replacing load/store architecture by non-instruction fetch-based designs for matrix multiplication, we reduced almost 100 percent of the dynamic power. Hence reconfigurable computing is the potential key to saving energy in battery-powered embedded systems...
Power-constrained systems, such as RF-powered smart cards are gaining increased significance in the embedded system's domain. These systems are highly susceptible to supply voltage drops caused by power peak regions that impact on the system stability. Power profile flattening mechanisms have emerged as an effective power peak countermeasure to enhance system reliability. In this paper we present...
ARM®'s success to date has been largely due to its remarkable performance/power (MIPS/Watt) rating, and this will likely continue to be its most critical benchmark for future applications. This paper considers the way in which attention to interdependent detail in intelligent voltage management, cache controller design, conditionally executable instructions, and interrupt control hardware contribute...
Modern embedded processors highly rely on the accuracy of branch predictors. Large predictors with complex prediction algorithms cause more power consumption of the embedded systems which are already power hungry. Power consumed by a branch predictor can be reduced by removing unnecessary predictor accesses. In this paper we present the design of a low power branch predictor that exploits the well-behaved...
In this paper, we propose a novel, non-invasive monitoring technique which allows rapid detection of timing-constraint violations in real-time embedded systems which have a time-triggered system architecture. The monitoring technique combines knowledge of the system's (static) task schedule and real-time measurements of the CPU power consumption in order to detect faults. We demonstrate the feasibility...
Embedded cache memories consumes a large percentage of the dynamic and static energy in System-On-Chip (SoC). Energy consumption expects to increase in advanced technologies. Write and read operations operate charging and discharging of large bitline capacitances. Multiplexors are introduced in 6 T-SRAM to reduce column size. Unfortunately read current is not reduced and even increases. Considering...
In this paper, we propose a self-reconfigurable platform which can reconfigure the architecture of DCT computations during run-time using dynamic partial reconfiguration. The scalable architecture of DCT computations can compute different number of DCT coefficients in the zigzag scan order to adapt to different requirements, such as power consumption, hardware resource, and performance. We propose...
Embedded systems assume an increasing importance in several biomedical applications. These applications present dissimilar requirements and characteristics, posing problems at the computing and communication levels. This paper proposes a general network based platform that follows a distributed approach based on a client/server architecture, in order to integrate embedded systems for biomedical applications...
This paper presents a soft error-tolerant architecture to protect embedded processors register files. The proposed architecture is based on selectively duplication of the most vulnerable registers values in a cache memory embedded beside the processor register file so called register cache. To do this, two parity bits are added to each register of the processor to detect up to three contiguous errors...
Coarse-grained reconfigurable architectures (CGRA) employ square or rectangular arrays composed of many computational resources for high performance. Though these array fabrics are mostly suitable for embedded systems including multimedia applications, they occupy large area and consume much power. Therefore, reducing area and power of CGRA is necessary for the reconfigurable architectures to be used...
Developing widely useful mobile computing applications presents difficult challenges. On one hand, mobile users demand fast response times, and deep relevant content. On the other hand, mobile devices have limited storage, power and communication resources. Caching frequently accessed data items on the mobile client is an effective technique to improve the system performance in mobile environment...
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