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This paper presents a novel systolic Coarse-Grained Reconfigurable Architecture for real-time image and video processing called P2IP. The P2IP is a scalable architecture that combines the low-latency characteristic of systolic array architectures with a runtime reconfigurable datapath. Reconfigurability of the P2IP enables it to perform a wide range of image pre-processing tasks directly on a pixel...
In this paper we present a novel approach to reduce the computation burden of a Field Programmable Gate Array based beamforming localization algorithm. This approach combines GCC (Generalize Cross Correlation) and DSB (Delay and Sum Beamforming). In this work, we reduce the position search spectrum by detecting the direction of arrival of the sound source before the computation of its position, this...
One of the main challenges for embedded system designers is to find a tradeoff between performance and power consumption. In order to reach this goal, hardware accelerators have been used to offload specific tasks from the CPU, improving the global performance of the system and reducing its dynamic power consumption. Enabling the use of accelerators could become a tricky task for embedded system designers...
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