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Optimum Power gating sleep transistor design and implementation are critical to a successful low-power design. The large magnitude of supply and ground bounces, which arise from power mode transitions in large power gating structures results in wrong functioning of the circuit. We propose a novel power gating technique showing the trade-off between wake-up time and supply noise. This technique is...
An ultra-low power adjustable triangle wave generator with a multi tunable amplitude and frequency is introduced in this paper. The proposed circuit consists of a Schmitt trigger and a current source. The overall nonlinearity of the TWG circuit is less than 2% in its current-to-frequency transfer characteristic. The tunable frequency and amplitude range are 10KHz to 40KHz and 0.1V-1.7V respectively...
Record 9nm half-pitch functional Transition-Metal-Oxide based Resistive Random Access Memory (TMORRAM) cell and the lowest reported 1μA programming current (Iprog, both Set and Reset) have been achieved with thermally oxidized sub-stoichiometric WOx and Nano Injection Lithography (NIL) technique. The unexpectedly low programming current at 9nm diameter has been examined in-depth, it offers potential...
The sample and hold amplifier plays an important role in the front end of an analog to digital converter. In this work, a low power, high resolution, and high speed sample and hold amplifier is presented. The architecture of the proposed mainly adapts the class A/B folded cascode amplifier with a gain boosting technique and a switch capacitor common mode feedback scheme. The performance comparisons...
Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper gives a brief overview of low power design principals, then focuses discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems. Finally we discuss low power optimization techniques at system and architecture...
The paper gives short overview of an efficient CMOS technology based current source realization and layout design. The current source output will be shortened square wave signal [1],[2] and [3]. The output current value can be selected from range 5 to 100μA. The current source layout design needs good matching, the geometry and temperature influence has been analyzed and the optimal geometrical structure...
We propose a compact design having low-power and high-speed EEPROM for touch-screen controller ICs. To optimize a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed which involves repeated high-voltage switching circuits inside the EEPROM core circuit. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed...
A potential drain/source swap problem in a traditional low-leakage charge pump under low supply is investigated and the design methodology and results of a low-voltage CMOS charge pump structure for phase-locked loop (PLL) applications are presented. Simulated in a 65-nm CMOS process, the structure is capable of reducing the static leakage current to the pA range while providing close to rail-to-rail...
In recent years, energy saving techniques have become critical in hardware designs, especially for mobile devices. This paper has reviewed several previous designs of double edge-triggered flip-flops, and has proposed a transmission-gate-based double edge-triggered flip-flop with a clock-gating function. Comparing to the previous work of double edge-triggered flip-flops, the proposed one saved 33...
This paper briefly reviews common state-of-the-art architectures of voltage regulators and their applicability to RFID. After that the design of a Low Drop-out (LDO) regulator using active resistances is presented, especially suitable for RFID applications. The chip is designed based on a 0.13 μm CMOS technology.
This paper demonstrates for the first time quantitative performance advantages of a zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T) with write-back schemes, which was previously recognized as the most area-efficient cell under large σVTH/VDD conditions. Since Z8T uses only 1T for each decoupled read-port, faster 2T differential sensing (D2S) can be implemented within...
A novel high-speed and low-power negative level shifter suitable for low voltage applications is presented. To reduce the switching delay and leakage current, a novel bootstrapping technique is designed for the level shifter. Furthermore, a pull-down driver is proposed to have high driving capability under different operation modes. The circuit has been designed in 130 nm 1.5 V/5 V triple-well CMOS...
This paper introduces a novel CMOS-memristor hybrid reconfigurable architecture, mFPGA. Different from the existing crossbar-based CMOS-memristor architectures, mFPGA mainly consists of lTlM-like structures that can be fabricated by using a CMOS-compatible process. These devices can efficiently establish FPGA block memories. More importantly, novel CMOS-memristor routing switches are developed to...
An ultra low-power, high linearity, wide swing, current sample-and-hold circuit is presented. The proposed circuit employs negative feedback, provides very low switching error and allows for class-AB operation. Sub-threshold CMOS devices are employed to realize all circuit building blocks which leads to ultra low power consumption and large dynamic range. Operating from a 0.65V supply, simulation...
This work addresses a new compact low-power highspeed output buffer amplifier topology for large-size LCD applications. The suggested buffer achieves fast driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities by exploiting the push-pull output sections of two basic complementary-type...
In this paper, we present a new design of TAS-MRAM, which is dedicated for the embedded applications. The Thermally Assisted Switching (TAS) approach allows the low power memory programming and Pre-Charge Sense Amplifiers (PCSA) enable the reliable, high speed and low power sensing. By using a TAS-MTJ spice model integrating the precise experimental parameters and CMOS 130nm technology, simulations...
This paper reports a 45 nm spin-transfer-torque (STT) MRAM embedded into a standard CMOS logic platform that employs low-power (LP) transistors and Cu/low-k BEOL. We believe that this is the first-ever demonstration of embedded STT MRAM that is fully compatible with the 45 nm logic technology. To ensure the switching margin, a novel "reverse-connection" 1T/1MT cell has been developed with...
Comparator-controlled power switch has been widely used to improve power efficiencies of discontinuous-conduction-mode (DCM) buck regulators. Some major design challenges are capabilities of the comparator to operate at low voltage and dissipate low power for low-voltage DCM buck regulators having high power efficiencies under light-load condition. This paper presents a new comparator with current-controlled...
Two-stage Class-A switched-opamp (SO) is the most popular module in previous low voltage low power SO sigma-delta modulators (SDM). The SO saves about 30%~40% of the total power since its output stage is just turned off at the integrating phase. To further increase efficiency a novel high power efficiency class AB current mirror SO is proposed in this paper. By turning off the entire SO together with...
Reducing leakage dissipation is becoming more and more important in low-power design. The dynamic energy dissipation reduction of adiabatic circuits using power-gating schemes has been introduced. In order to reduce leakage losses of the adiabatic circuits using power-gating schemes under deep submicron process, this paper proposes a MTCMOS (Multi-Threshold CMOS) power-gating scheme for adiabatic...
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