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Operating CMOS circuits at subthreshold supply voltages is an attractive solution for substantial energy reduction, at the expense of strong timing performance degradation, for a broad range of battery operated appliances. One of the challenges of this approach in current technology nodes is the reduced available noise margin when operating at low supplies. This paper evaluates the Static Noise Margin...
Vertical GaN power semiconductors promise higher power with faster switching speeds but the development of this technology has been slowed. This is due to the expense and lack of familiarity with GaN substrates. This paper will detail the functionality of HRL's cutting-edge vertical GaN transistor which is mounted onto a specially made PCB and tested. The testing consists of a static characterization...
Lateral GaN-on-Si HEMT technology enables integrated high-voltage half-bridges with gate drivers. However, the capacitive coupling through a common conductive substrate influences switching characteristics. The measured hard-switching turn-on time with floating substrate increased to over 16 ns as compared to conventional source-connected substrate (1 ns), switching 300 V/4A with GaN ICs comprising...
This paper presents a clock-feedthrough compensation technique for bootstrapped switches. The proposed technique utilizes a dummy transistor to generate a reverse voltage, which compensates the input-dependent error caused by clock feedthrough effect of sampling switch. Simulation result shows the differential sampling error of bootstrapped switch reduces from 7.2mV to 1.4mV for the worst case, operating...
In this paper we present a new architecture for thermometer-coded digital-to-analog converters (DAC) that are used as a part of segmented DACs. The size of the binary-to-thermometer decoder tends to grow relatively large compared to the DAG when the number of input bits increases. We propose an architecture that utilizes PMOS current source transistor and moves the switching logic inside the current...
This paper presents a detailed noise and non-linearity analysis of a 10-bit 1.2Vppd 50MS/s charge-injection based SAR-ADC designed in a 65 nm low power process. Being more area-efficient in contrast to a conventional capacitor DAC, a charge-injection-cell-based DAC allows to reuse its DAC cells during binary search. Based on extensive calculations and transistorlevel simulations, the charge-injection...
An analysis of high speed sample and hold circuit in different structure is presented. Performance and area comparison between two type of sample and hold circuit in low voltage is done. These different type of circuits are simulated and layout designed in 55nm CMOS technology. Both the structures based on a bootstrap switch that can acquire analog wave forms at sampling rate of 100MHz with 10 bit...
The last 10 years have seen the rise of new NVM technologies as alternative solutions to Flash technology, which is facing downsizing issues. Apart from offering higher performance than the state of the art of Flash, one of their key features is lower power consumption, which makes them even more suitable for the IoT era. But one of the other main concerns regarding IoT is data security, which is...
This paper describes a 9-bit Successive Approximation Register Analog to Digital Converter (SAR-ADC) design in CMOS technology, particularly I4T, 0.35 μm, 45 V, used in automotive industry for sensor application. There are the individual analogue components of the SAR-DAC descibed in this paper: the Comparator, the R-2R Digital to Analog Converter (DAC) and the Operational Amplifier (OPA). The functionality...
Integrated Voltage Regulators (IVRs) have become a viable solution for microprocessor's power delivery. The active parts of the most recent IVRs are built in deep-submicron CMOS technologies and use stacked transistors to allow for the use of advanced low voltage devices with superior switching performance compared to the higher voltage long-channel devices. This paper evaluates three different topologies...
In this study, a mode transition scheme between a single phase half bridge 2-level voltage source converter (VSC) and a 3-level T-type VSC is proposed. The efficiency of 3-level T-type VSC can be increased by the mode transition scheme. The mode transition scheme select the efficient operation method between a 2-level and 3-level VSC. The 2-level VSC or 3-level VSC operation method are selected depending...
This paper presents the design insights for the implementation of a monolithic radio frequency (RF) Class-E power amplifier for WLAN applications. The proposed high efficiency monolithic CMOS class-E power amplifier showcases the effective RF performance enhancement which is composed of two-stage structure and adopts a differential cascode topology with self-biased technique. The differential stage...
We introduce a CMOS computational fabric consisting of carefully arranged regular rows and columns of transistors which can be individually configured and appropriately interconnected in order to implement a target digital circuit. Termed Field Programmable Transistor Array (FPTA), this novel reconfigurable architecture enables several highly-desirable features including (i) simultaneous storage of...
Multiple independent-gate field effect transistors (MIGFETs) have great potential for digital integrated circuits. In this work, we demonstrate that conventional binary adder architectures may benefit from the use of MIGFET devices. As case studies, we have designed ripple-carry adders (RCA) and parallel-prefix adders (PPA), where circuit area and performance optimizations are explored. Different...
Although Network-on-Chips (NoCs) are fast becoming pervasive as the interconnect fabric for multicore architectures and systems-on-chips, they still suffer from excessive static and dynamic power consumption. High dynamic power consumption results from switching and storing data within routers/links while excess static power is consumed when routers and links are not utilized for communication and...
With the saturation of the Flash memory technologies scaling under the 20nm nodes, new technology opportunities are explored by both industrial and academic research teams. Resistive switching memories are today seen as the most promising replacement candidate for both embedded (NOR) and stand-alone (NAND) flash memories. The native Back-End-of-Line (BEoL) integration enabled by the RRAM technologies...
More and more power electronics applications utilize GaN transistors as they enable higher switching frequencies in comparison to conventional Si devices. Faster switching shrinks down the size of passives and enables compact solutions in applications like renewable energy, electrical cars and home appliances. GaN transistors benefit from ∼10× smaller gate charge QG and gate drive voltages in the...
In this paper a SPICE (Simulation Program with Integrated Circuit Emphasis) implementation of a memristor model able to describe the major and minor current-voltage loops in bipolar resistive switches is reported. In particular, this work addresses the implementation of one transistor-one resistor (1T1R) structures for RRAM applications by means of SPICE simulations. Specifically, the dependence of...
Analog-to-Digital converters plays vital role in medical and signal processing applications. Normally low power ADC's were required for long term and battery operated applications. SAR ADC is best suited for low power, medium resolution and moderate speed applications. This paper presents a 10-bit low power SAR ADC which is simulated in 180nm CMOS technology. Based on literature survey, low power...
This paper presents a 2/3 step-down switched-capacitor DC-DC converter with integrated NMOS-LDOs in both charging and discharging phases to suppress the output voltage ripple. A gate driving technique implementing adaptive gate slope and gate pre-charge is proposed to reduce the switching noise during phase transitions and assist the turn-on of the regulation transistors, respectively. Good load regulation...
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