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The Software/Hardware Implementation and Research Architecture (SHIRA) is a C to hardware toolchain developed by the Computer Architecture Research Group (CARG) of the University of Ottawa. The framework and algorithms to generate the hardware from an Intermediate Representation (IR) of the C code is needed. This paper presents the conceiving, design, and development of a module that generates the...
The main obstacle for the wide acceptance of UML and SysML in the design of electronic systems is due to a major gap in the design flow between UML-based modeling and SystemC-based verification. To overcome this gap, we present an approach developed in the SATURN project which introduces UML profiles for the co-modeling of SystemC and C with code generation support in the context of ARTiSAN Studio®...
Embedded systems are targeted for specific applications under constraints on relative timing of their actions. In this paper, we proposed a co-synthesis approach to hardware/software (HW/SW) co-design for embedded system based on Dynamic Data Flow (DDF). Firstly, we introduced the theory of DDF and presented a methodology of designing embedded system on system-level that depends on decomposing DDF...
The flow of universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, hardware part and software part of a design are described with SystemVerilog and SystemC, respectively after hardware/software partitioning. The functional interaction...
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) with manual hardware design. Recent research has demonstrated that soft processors augmented with support for vector instructions provide significant improvements in performance and scalability for data parallel workloads...
Rapid HDL is a hardware definition language developed in C# for the Microsoft .Net platform. Rapid HDL unifies digital FPGA hardware development and co-software integration. Hardware is scripted using reusable software objects, communication between hardware and software is automatic, and synthesis is automated using a free tool chain. Rapid HDL represents 18,000 lines of code and is freely available...
Reconfigurable SoPC is an advanced component for distributed and real time applications. Co-design of HW and SW for SoPC are both in hierarchy and hybrid. For hierarchy, a SoPC application design may be concerned to C language, Assembly, Hardware Description Language HDL and PLD hardware. For hybrid, the SoPC hardware is built by HDL programming on PLD in some design level. That means the hardware...
High-performance FPGA accelerating software applications are a growing demand in fields as communications, image processing, and scientific computing among others. Moreover, as the cost per gate of FPGAs declines, embedded and high-performance systems designers are being presented with new opportunities for creating accelerated software applications using FPGA-based programmable hardware platforms...
Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffers due to the use of C constructs and coding practices that are not appropriate for hardware. Most previous approaches to addressing this problem require drastic changes to coding practice. We present an approach that instead...
This paper describes an innovative hardware/software co-verification platform, based on an embedded logic analyzer (ELA) in FPGA emulator, for system-on-a-chip. With the general-purpose ELA, the platform is rich in reusability, which reduces the expense of SOC verification. By offering the interface, image of design under test (DUT) and virtual channel, the platform plays the role as glue, which integrates...
This paper presents a new architecture of scaleable FFT processor using hardware/software codesign technique for orthogonal frequency division multiplexing (OFDM) systems. The architecture uses a radix-4 butterfly node located on both hardware and software processing elements. We employ an in-place memory strategy, resulting that the butterfly inputs and outputs can be stored at the same memory location...
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