Search results for: Myoung-Keun You
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The implementation of a verification environment to check the behavior of a device-under-test using SystemC infrastructure is presented in this paper. SystemC is generally adopted in a system-level design methodology because of the capability of architectural model description and hardware/software co-design. The verification system implemented in this paper can explore design space using SystemC...
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The flow of universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In this paper, hardware part and software part of a design are described with SystemVerilog and SystemC, respectively after hardware/software partitioning. The functional interaction...
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2009 IEEE 8th International Conference on ASIC > 694 - 697
This paper introduces our experience in verifying the operation of each systolic array before and after reconfiguration using Truss. Truss is an implementation of an open-source verification infrastructure based on layer approach. Reconfigurable systolic array for solving either single-source shortest path problem or 0-1 knapsack problem is chosen as a reconfigurable device-under-test. One systolic...
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2009 IEEE 8th International Conference on ASIC > 1310 - 1313
A verification environment which is based on a constrained random layered test bench using SystemVerilog OOP is implemented in this paper to verify the functionality of DUT designed with synthesizable constructors of SystemVerilog. Although the uses of multiple inheritance in OOP appear to be less common than those of single inheritance, multiple inheritance is useful for creating class types that...
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2007 7th International Conference on ASIC > 1245 - 1248
A C-to-SystemC synthesizer which processes the input behavior according to high-level synthesis, and then transforms the synthesis result into SystemC code is implemented in this paper. In the synthesis process, the input behavioral description in C source code is scheduled using list scheduling algorithm and register allocation is performed using left-edge algorithm on the result of scheduling. In...
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The implementation of a simple hardware emulator platform using limited resources is presented in this paper. The emulator platform consists of an evaluation board based around ARM processor core and a starter lit loaded with an FPGA chip, and uses tools from open-source software. The software part of the emulator is executed by ARM processor after being loaded into SRAM on evaluation board, and hardware...
