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This paper presents a methodology for reducing interconnect resources in reconfigurable platforms such as field-programmable gate arrays (FPGAs). This methodology utilizes the techniques developed for the buffer-based dataflow, a new design representation suitable for implementing data-centric applications in a reconfigurable platform. In a buffer-based dataflow, nodes correspond to processing blocks...
As semiconductor manufacturing continues towards reduced feature sizes, yield loss due to process variation becomes increasingly important. To address this issue on FPGA platforms, several variation aware design (VAD) methodologies have been proposed. In this work we present a practical method of process variation characterization (PVC) to facilitate VAD using only intrinsic FPGA resources. The scheme...
The following topics are dealt with: computer aided design; system estimation; system evaluation; design optimization; manufacturing-aware design; analog signal verification; mixed signal verification; process variation; digital system; embedded system; FPGA synthesis; power-sensitive condition; reliability analysis; memory system scheduling; physical synthesis; yield analysis; quality analysis; nanometer...
Leakage power is a key challenge in VLSI design, and process variations have aggravated the problem. Interconnects have become very critical in modern VLSI designs and have started to play a major role in determining the power and performance of a design. Certain VLSI circuits such as FPGAs are interconnect dominated, such that their performance and power are largely governed by the interconnects...
The latest generation of FPGA devices offers huge resource counts that provide the headroom to implement large-scale and complex systems. However, this poses increasing challenges for the designer, not just because of pure size and complexity, but also to harness effectively the flexibility and programmability of the FPGA. A central issue is the need to integrate modules (IP blocks) from diverse sources...
Routing switches are one of key challenges in FPGA Design field. There are several works performed on routing switch design, but the effect of wires in interconnection rarely considered. In this work, switch design methodologies have been investigated. Among these methods, a modified routing switch is proposed which has less delay and power with notice the wires effects.
FPGA structures are widely used due to early time-to-market and reduced non-recurring engineering costs in comparison to ASIC designs. Interconnections play a crucial role in modern FPGAs, because they dominate delay, power and area. Multiple-valued logic allows the reduction of the number of signals in the circuit, hence can serve as a mean to effectively curtail the impact of interconnections. In...
Recently, FPGAs have been integrated into HPC clusters in order to boost computational performance while reducing power consumption. However, performance and effective logic utilisation is usually limited by the number of inter-device pins and most importantly the interconnection architecture. Mesh interconnection in particular suffers from the pin-limitation problem. The concept of Virtual Wires...
Recently, the VRC (virtual reconfigurable circuit) has become a mainstream solution for EHW (evolvable hardware) research. In this paper, A LUT-based VRC model is proposed, which can be applied for random logic function evolution. Different kinds of LUTs with appropriate interconnections were studied on a FPGA-based platform. Research were also performed in this platform to compare with the current...
Energy-performance tunable circuits enable the user to adjust the energy and performance of a chip after fabrication to suite the particular application, thus increase the overall power efficiency of the chip. Two tunable interconnect architectures are proposed. Pseudo-static interconnect achieves the same performance as static interconnect while consuming only 65% as much energy and provides 2X wider...
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper, we present the design of such an accelerator for the kth nearest neighbor thinning problem on an XD1000 reconfigurable computing system. The design leverages IMORC, an architectural template and highly versatile on-chip...
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-to-chip interconnect which is particularly used in AMDs novel Opteron processor series. As it is an open protocol, a broad application range exists ranging from southbridge chips over closely coupled accelerators to add in cards. Its...
One of the main challenges in building reconfigurable asynchronous architectures is the design of the reconfigurable interconnect scheme. An asynchronous channel connecting a sender to multiple receivers cannot be split or shared between the receivers without additional complex circuitry to acknowledge every transition on the channel. The technique used in existing asynchronous reconfigurable architectures...
In this paper, we present a new multilevel hierarchical (tree-based) coarse-grained FPGA architecture. This architecture comprises two unidirectional interconnects, a downward interconnect and an upward interconnect. The proposed architecture can support various kinds of coarse-grained blocks. These coarse-grained blocks are defined using an architecture description file. A new software flow has been...
Increasing on-chip power densities with aggressive technology scaling has led to a low-power FPGA fabric with dual supply voltages. Such low-power techniques coupled with the heterogeneity of components on a FPGA have led to non-uniform aging of components due to temperature and voltage dependent failure mechanisms. In this paper, we present techniques in placement and routing stages of the design...
In this paper, we first recap the rationale beyond the (non)-acceptance of multi-valued logic in implementing FPGAs so far, explaining the most critical technological and tool support details. Then, we outline the critical applications of FPGAs (e.g., emulation) where the non-binary nature can be exploited by MVL implementation. Finally, we highlight the most significant opportunities that present...
For large-scale circuit emulation with using a multi-context FPGA (MC-FPGA), a circuit is divided into multiple sub-circuits, each sub-circuit is assigned to a context., and the MC-FPGA sequentially executes all the contexts one by one. So, the total execution delay is the sum of the delays of the contexts. It is, therefore, said that the total execution delay of the MC-FPGA increases proportional...
On-FPGA communication is becoming more problematic as the long interconnection performance is deteriorating in technology scaling. In this paper, we address this issue by presenting a new wave-pipelined signaling scheme to achieve high-throughput communication in FPGA. The throughput and power consumption of a wave-pipelined link have been derived analytically and compared to the conventional synchronous...
The proposed XLE model will enable us to calculate the delay of FPGA interconnect and determine closed form expressions for optimal transistor size, sensitivity and a minimal bound on delay. We will further extend it to cover process variations, resulting in a tool that can compare the statistical properties of different architectures. The models are simple and relatively technology independent and...
The division of an application between a conventional processor and an acceleration card with FPGA chips has been proved as a suitable way for an acceleration of computationally intensive tasks. In such applications, the designer usually has to implement an interconnection between components placed in FPGA and the host system bus. This task is often complicated by different requirements of user components...
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