The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Planar fully-depleted SOI technology with ultra-thin body and buried oxide presents a platform for an energy-efficient design in deeply scaled technologies without major changes in the bulk-CMOS design infrastructure. Good control of short-channel effects with thin transistor body offers a possibility to reduce the supply voltage. Thin buried oxide provides threshold tuning via body bias. Overall...
This paper presents a new SRAM memory cell in Double Gate MOS technology. It's a reconfigurable 6T-4T that takes benefit of the advantages of both 6T and 4T SRAM cells. The cell improves both read stability and write-ability, without adding any transistor or external signal, compared to conventional 6T SRAM cell. The write ability is improved by a factor of 64% and the stability in read mode by a...
This work is aimed at a novel program method that is assisted by light for capacitorless 1T-DRAM based on parasitic bipolar junction transistor operation. Experimental results clearly show that a flash of light triggers a distinctive binary memory state in the capacitorless 1T-DRAM. During the operation of the 1T-DRAM, the gate voltage is sustained at a negative, constant value. The sensing margin...
In this paper, we propose a subthreshold SRAM cell structure which can be read differentially. The main advantage of the cell is its high read current while the static noise margin and power consumption are reasonable. The cell is suitable for high performance applications where the speed is of prime concern. To assess the efficiency of the proposed cell, we compare its characteristics to three subthreshold...
In this paper, a new compact, robust and low leakage 4T SRAM cell is proposed. It is based on an original concept of multi-VT thin buried oxide (BOx) fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs with ground plane (GP) in 45 nm technology node. The stability of the cell reaches 20% of VDD and the cell leakage is 13 pA. A minimum cell area of 0.209 mum2 with specific 45 nm SRAM design rules...
The author invented a trench-capacitor dynamic-random-access memory (DRAM) cell and applied the Japanese patent in 1975. The first trial development of trench-capacitor DRAM cell was presented in 1982 in 1-Mbit DRAM era. This might be the first attempt to utilize vertical wall of silicon substrate for metal-oxide-semiconductor (MOS) structure. Subsequent to this trial various kinds of vertical-channel...
The degradation of SRAM stability with gate length and supply voltage scaling is a serious concern [1-7]. In this work, we analyze the impact of gate-underlap design [8-9] on the performance of 6-T SRAM cell, based on independently addressable 22 nm Double Gate (DG) SOI MOSFETs for low voltage operation. The trade-offs associated with read/write requirements have been evaluated in terms of eight performance...
In this work, we have compared different FB-RAM architectures. Whereas highly doped PDSOI devices show high programming window and retention times for long channel devices, the SOI FinFET devices with WFIN=25 nm can be scaled down to LG=50 nm while still maintaining high cell margins and retention times. For the latter devices optimization of the write and especially read bias conditions is needed.
A capacitor-less one-transistor DRAM cell with surrounding gate MOSFET with vertical channel (SGVC) using gate-induced drain leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact ionization current, the write operation with GIDL current provides high sensing margin owing to higher potential barrier between body and source. To confirm...
Multi-gate devices are expected to enable continued scaling beyond the 32nm node in part due to their improved gate control of the channel versus planar MOSFETs. Static random access memory (SRAM) scaling, which requires increasing design margins despite decreasing layout area, may motivate the transition to a multi-gate architecture. Tri-gate bulk devices are an attractive multi-gate option because...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.