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The trend towards multi-die flip chip packaging favors the incorporation of a qualified manufacturingcompatible rework process to remove and replace individual defective die. Inherent to the rework process is an electrical verification step that effectively identifies the defective device without compromising the integrity of an otherwise perfectly functional device. Unfortunately, the very feature...
For the last decade, paraelectric BaxSr1−xTiO3 (BST) thin films have been especially studied to fabricate MIM capacitor for capacitance tuning applications. This paper describes the mechanisms of cracks apparition under BST stacked MIMIM capacitors (Metal Insulator Metal Insulator Metal) built on silicon substrate. The methodology used in this study to have a further understanding of this phenomenon...
One-shot micro-valves are key to applications that require leak-proof sealing of micro-cavities before they are irreversibly triggered to expose the cavity content to the outside environment. Here, we report a novel micro-scale one-shot valve made of graphene transferred on to silicon-nitride (SixNy) membranes. The valve triggers thermo-mechanically in 15.4±3.9 msec consuming 142.1±13.5 mW electrical...
This paper summarizes key learnings on 20/16nm CPI (Chip-Package-Interaction) challenges at 100um pitch and below to support ever increasing performance/cost/form factor demands for high performance mobile SoCs. CPI solutions for two types of Cu pillar interconnects using mass reflow and thermal compression type assembly process respectively are studied in technology development/production, and separate...
Initially flat silicon wafers are prone to warp due to the high levels of intrinsic stress of deposited films, particularly metallic films. Processing and handling of warped wafers in the fab is a challenge. One of the ways to control the degree of warpage is by limiting the amount of metallization allowed on the wafer. However, this imposes a constraint on the silicon designers, and can lead to decreased...
A three-dimensional (3-D) LSI has many lots of through-Si vias (TSVs) and metal microbumps to achieve electrical connections between stacked thinned LSI chips, and also has organic adhesives to obtain completely bonded thinned LSI chips. However, these elements, especially microbumps and organic adhesives, induce static and dynamic local bending of the thinned LSI chips. In this study, for the first...
Thin crystalline silicon solar cells, on the order of a few to tens of μm thick, are of interest due to significant material cost reduction and potentially high conversion efficiency. These thin silicon films impose stringent mechanical strength and handling requirements during wafer transfer, cell processing and module integration. Quantitative mechanical and fracture analyses to address reliability...
In this paper, the stretchable interconnect is taken as the research object and its reliability has been analyzed by simulations. Polydimethylsiloxanes (PDMS), as a hyper elastic material, is used here as the stretchable interconnect substrate because of their high elastic property and high stretchability. Traditionally, metals are still the best options to realize the interconnections due to good...
In order to adapt the development of the Integrated circuit, a three-dimensional chip stacking structure was developed to achieve high performance, low power consumption and small packaging size. The 3D structure was divided into four major parts, including through silicon via, isolation wall, conductive line, and metal bump. We focused on the reliability of the metal bump in this kind of three-dimensional...
We reveal the mechanism of assembly stress in pad areas of flip chip package by using our new local stress evaluation technique in μm resolution. The technique is designed to evaluate the characteristic change of high-k/metal gate transistors (Trs) that are arrayed in μm pitch.
This paper presents the study on the effect of bump structure, chip pad structures and die thickness of a large die Cu/low-k chip for improving assembly performance on organic buildup substrate. After assembly with the initial interconnection design, metal cracks at RDL were found for the conventional SnAg bump and Cu post samples. In order to improve the bump structure design a thermo-mechanical...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
Unlike HBM and MM, CDM robustness is highly dependent on IC layout and packaging. Therefore, IC companies mimic IC IO rings on IO-TEG test chips to select the most appropriate CDM protection concepts (correlation from IO-TEG to final IC??s). This publication highlights pitfalls for this approach. Ensuring consistent substrate and Vss connections drastically improve the correlation.
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