Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
Spurious oscillations in the low frequency region (below 100kHz) were investigated in InGaP/GaAs HBT devices and circuits. These low frequency oscillations (LFOs) are predominantly activated by the field across the semi-insulating GaAs substrate located between the subcollector and backside metal (of an emitter-up device). Several experiments were conducted to control and eliminate LFOs by floating...
The rapid development of semiconductor technology and multi-function demands of end products has driven IC foundry industry toward 7nm node process, and even next generation of 5nm. The I/O pitch of chip is reduced accordingly but the Build-up layer of IC carrier is still too large to fit interconnects. In order to overcome the gap of I/O pitch between IC chip and carrier, the interposer technology...
We have developed the epitaxial growth technology of Ge1−xSnx and related group-IV materials. The crystalline properties and energy band structure have been investigated for integrating group-IV semiconductors into Si ULSI platform.
The original purpose of the Re-Distribution Layers(RDL) was to assist in the adaption of metal bumping and flipchip packaging technologies, by the addition of the metal anddielectric layers onto the wafer surface to re-route the legacydesigned irregular peripheral I/O layout, into a new area arraybond pads layout to facilitate a balanced metal bumps and flipchip bonding. The redistribution layer technology...
Cutting of packaged IC involves removal of different materials including semiconductor, metal and polymeric compound. Dicing saw has long been utilized to perform the task in regular (rectangular) shape. However, chipping and micro cracking at the edges and deteriorated strength of the packaged die are still problems to be solved. Laser has the advantages of being capable of cutting irregular shape...
New applications for passive UHF RFID systems, such as tagging small and expensive metal objects, impose strict requirements on the size of the tag antenna and the read range of the system. Thus, miniaturized tags that achieve read ranges of several meters are of major interest for these applications. In this contribution, the design of a small antenna to tag metallic items is presented. It achieves...
Current state-of-the-art technologies for retinal prosthetics suffer greatly from complicated IC packaging with high lead count because there is the lack of high density and high lead-count connection. To overcome this challenge, we develop here a packaging technique that utilizes a flexible parylene pocket with metal pads to house a chip for aligned connection. This reported pocket can be designed...
A robust verification methodology for 3D-IC design is presented. This approach addresses the challenge of delivering a familiar verification solution with minimal disruption to existing design and verification flows. The proposed method provides a generic framework that allows users to specify their own 3D-IC design stacks for verification with TSVs, flip-chips or wire-bonded dies.
This paper describes a configurable passive voltage contrast (PVC) checker for fault identification. The checker uses an on-line trace technique to query connectivity of design layout features downward, and color coded the checked features according to pre-defined terminations. The checker was used for fault identification on a scan based design. The emulated PVC behavior expedites comparison to scanning...
Most of the wafer level 3-D technologies are using Through-Silicon Vias (TSV). The main barriers for these approaches are high cost, issues with electrical isolation within the Si via and the need of high investments for new equipment which is not used in WLP up to now. A planar integration technology of ultra-thin bare dice in a Wafer-Level Thin Film technology yield to a high-dense module will be...
Implementation of a high quality spiral inductor on silicon substrate is a long lasting challenge for the microfabrication researchers; in this paper a new spiral inductor which is compatible with the standard IC technology is proposed. This new inductor shows more quality factor and higher resonance frequency even though the overall inductance value remains almost the constant in compare with the...
Three dimensional memory systems has been argued as a potential pathway in solving the ever growing difference between comparative speeds of CPU and memory systems. In this paper, we describe a three-tier, three-dimensional SRAM macro that has been designed and fabricated in a 0.18 um FD-SOI CMOS technology. 3D stacking is found to improve wire latency as compared to planar memory structure although...
The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
Graphene is a possible candidate for advanced channel materials in future field effect transistors. This presentation gives a brief overview about recent experimental results in the field of graphene transistors for future electronic applications.
Advances in micromachining technology can facilitate the integration of SAW (Surface Acoustic Wave) devices and CMOS circuitry on IC scale substrate for Monolithic fabrication. The optimal design and performance of these filters can be reached by using new Smart materials. The key component in the structure of the SAW device is the piezoelectric materials used which depends mainly on some important...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
An electrical overstress failure induced by a latch-up test is studied in high-voltage integrated cricuits. The latchup test resulted in damage to the output NMOSFET due to snapbach and also resulted in a latch-up in the internal circuits. These mechanisms are analyzed and solutions are proposed to avoid the triggering of the output NMOSFET and the resulting latchup issue.
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.