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Authors offer the way of formation of self-checking concurrent error detection systems of combinational circuits based on Boolean complement method with “1-out-of-5”-code. This code's checker needs five code words for full test and has low technical realization complexity. This allows organization of concurrent error detection system with reduced structural redundancy compared with duplication method...
Aliasing in the test response compaction is an important source of fault coverage loss. Methods to avoid the aliasing generally require modification of the compactor to some extent. This can lead to a higher compactor complexity and consequently to higher area overhead, longer signal propagation delays, etc.We propose a novel method, the Zero-aliasing ATPG (ZATPG), which is able to reduce the aliasing...
The improvement in Integrated Circuits density increases the fault occurrence probability. To ensure proper operation of critical systems, circuits testing becomes a task of extreme importance. Over the years, several methods have been proposed to optimize ATPGs (Automatic Test Pattern Generation). The optimization in test pattern generation aims to reduce the set of test vectors to be applied to...
Functional, at-speed vectors continue to provideadded value to the testing community as circuit complexityrises. Complex defects may escape traditional scan vectors andthus often require at-speed patterns. However, generation offunctional/sequential vectors is an extremely challenging problem. Previous methods rely on formal models of the RTL or calls togate level ATPG, both of which are computationally...
A new method of high level test generation based on the concept of test groups to prove the correctness of a part of system functionality is proposed. High-level faults of any multiplicity are assumed to be present in the system, however, there will be no need to enumerate them. Unlike the known approaches, we do not target the faults as test objectives. The goal of using the test groups is to extend...
The paper presents a new structural fault collapsing method with linear algorithmic complexity to reduce the search space for test generation and fault diagnosis in digital circuits. The method is based on the two phase topology analysis of the circuit description. The first phase of fault collapsing is carried out on the gate level during superposition of Binary Decision Diagrams (BDD) of logic gates,...
In this paper authors consider the problem of concurrent error detection (CED) system of combinational circuit with unidirectionally independent outputs design using modulo codes with the summation. Considering of error detection features of modulo codes with the summation allows designing CED systems with reduced complexity comparing with the ones based on the classic Berger code. Authors determine...
Full scan designs are widely used for their indisputable benefits of predictably high test coverage, diagnosis and debug. However, for high-performance designs the cost of scan - area and delay - is not acceptable and partial scan is used instead. Unfortunately, partial scan significantly increases test generation complexity. We define a structured partial scan design methodology and specific test...
Analyzing logic masking effects in combinational circuits is an important key to evaluate soft error tolerance of circuits. Logic masking effects can be analyzed exactly with employing fault simulation. The computing complexity of a fault-simulation-based algorithm, however, is proportional to the square of circuit size, which might be unacceptable to achieve a scalable analyzer. On the other hand,...
The paper presents a new structural fault-independent fault collapsing method for test generation based on the topology analysis of the circuit, which has linear complexity. Fault collapsing is carried out by superposition of binary decision diagrams (BDD) for logic gates, which is used for constructing structurally synthesized BDDs (SSBDD). A new class of SSBDDs with multiple inputs (SSMIBDD) is...
The paper presents a new structural fault-independent fault collapsing method based on the topology analysis of the circuit, which has linear complexity. The minimal necessary set of faults as the target objective for test generation is found. The main idea is to produce fault collapsing concurrently with the construction of structurally synthesized binary decision diagrams (SSBDD) used for test generation,...
Rewiring is known to be a new class of logic restructuring technique at least equally powerful in flexibility compared to other logic transformation techniques while being wiring-sensitive, a property particularly useful for interconnect based circuit synthesis processes. One of the most mature rewiring techniques is the ATPG-based Redundancy Addition and Removal (RAR) technique which adds a redundant...
This paper presents an exact and efficient Critical Path Tracing algorithm targeting fault simulation of both Transition and Stuck-at faults. The complexity of the proposed algorithm is linear in the number of gates traced during the path tracing process. Experimental results show the efficiency of the proposed approach on a set of benchmark circuits.
Methods of designing of totally self checking sequential machines are presented in this paper. The main problem in TSC sequential machines (TSC SM) designing is synthesis TSC functional excitation circuit. Formal condition of self testing (ST) property for AND-OR structures are given. New method of circuit minimization is presented and ST of minimized circuits is proofed. We also present a methodology...
As a result of shrinking device dimensions, the occurrence of transient errors is increasing. This causes system reliability to be reduced. Thus, fault-tolerant methods are becoming increasingly important, particularly in safety-critical applications. In this paper a novel fault-tolerant method is proposed through combining time redundancy with information redundancy to reduce hardware complexity...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
Field programmable gate arrays (FPGAs) are getting more and more attractive for military and aerospace applications, among others devices. The usage of non volatile FPGAs, like Flash-based ones, reduces permanent radiation effects but transient faults are still a concern. In this paper we propose a new methodology for effectively measuring the width of radiation-induced transient faults thus allowing...
One effective fault injection approach involves instrumenting the RTL in a controlled manner to incorporate fault injection, and evaluating the behaviour of the faulty RTL whilst running some benchmark programs. This approach relies on checking the effects of faults whilst the design is executing a specific binary image, and therefore the true impact of the fault is limited by the shadow of the program...
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
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