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In this work, a 3-D IC architecture is proposed that composes an odd tier-number to provide enough flexibility to a circuit block at a specific tier to connect blocks at all other tiers. For a three-tier structure, it provides flexibility to a circuit block at the bottom or top layer in order to simultaneously connect blocks assigned to other layers. Such architecture would result in lower thermal...
Three-dimensional (3-D) integration with through-silicon-vias(TSVs) has been laid high expectations in overcoming further miniaturization obstacles faced by conventional 2-D integrated circuits (ICs) and solving compatibility problems of system integration among heterogeneous chips. We have proposed a simple but feasible process named “vacuum-assisted spin coating” for the fabrication of high aspect-ratio...
We demonstrate a front-side process integration method to insert high-density 1.2um diameter Tungsten (W) Through Silicon Vias (TSVs) into advanced-node logic wafers after metal-4. This late-TSV-middle approach offers the ability to build 3D technology into commercially available 90nm-node CMOS, while avoiding many of the challenges associated with TSV-last integrations. We also demonstrate a TSV-reveal...
In this paper, we explore the design considerations of two approaches to 2.5-D integration (silicon interposer and bridge-chip) from a thermal perspective and compare to 3-D ICs. Moreover, the impact of die thickness mismatch and die spacing are investigated in 2.5-D systems. We conclude that the die dissipating the largest power should be the thickest in a multi-die package. Larger lateral spacing...
As the density of 3D interconnects is increasing exponentially when scaling to lower levels of the interconnect wiring, in most cases 3D interconnect pitches of 5 μm and below will be required. Dielectric wafer to wafer bonding with via last integration can offer these interconnect densities. Wafer-to-wafer alignment and its impact on via last alignment are discussed. By taking into account current...
The backside via-last through silicon via (TSV) process is a simple and cost-effective approach for three-dimensional integration. However, it has two problems: (1) the notching near the bottom corners of TSVs and (2) the reaction product generated by the etchback step. To overcome these problems and increase TSV yield, we previously proposed a via-last TSV process using notchless Si etching and wet...
Three-dimensional IC (3D IC) is a promising method to enhance IC performance. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive. An epoxy-based material, so-called underfill, has been widely used to fill the gap between several chips....
In this paper, we proposed a novel stacked layer of liner structure around the TSV's and verified its performance on noise coupling between them. The performance of proposed structure with different materials and thickness were optimized and verified with respect to the noise coupling reduction. The obtained results show almost equal noise reduction performance of around 40% with the Teflon-Cu-Teflon...
An advanced TSV metallization scheme, featuring a high conformal ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high throughput copper ECD filling is presented. Because of the high conformality of the WN barrier and NiB seed, very thin layers can be deposited, reducing the manufacturing cost significantly, while still guaranteeing continuous barrier/seed layers all...
Physically meaningful and easy-to-use analytical predictive stress models are developed for a through-silicon-via (TSV) design using theory-of-elasticity based approach. Two extreme cases of the TSV height-to-diameter ratios are considered: disc-like vias, with the aspect ratios below 0.25 (plane stress approximation can be employed in this case), and rod-like-vias, with aspect ratios, above 2.5 (plane...
A new TSV formation methodology based on advanced Directed Self-Assembly (DSA) with nanocomposites consisting of nano metal particles and block-co-polymers is proposed in this paper. Cylindrical nano-ordered structures are formed in Si deep holes through phase separation of polystyrene-block-poly methyl methacrylate polymers (PS-b-PMMA). The impact of molecular weight of the polymers, composition...
In this paper we will discuss a method of fabricating a 0.8um and 1.2um diameter, 10um deep tungsten through-silicon-vias (TSV) from the backside of a 200mm silicon wafer at 4um and 2um pitches. These high-density tungsten TSVs connect to a thin copper backend, such as a metal 1 layer (M1) which can be as thin as 1000Å. We've applied this technology on a CMOS wafer from a high volume foundry and inserted...
In this paper, performance of noise coupling is studied using conventional SiO2 liner and Teflon AF1600 liner over different TSV structures (using only liner and liner surrounded by p+ guard ring). We have taken an optimized liner thickness of 0.15 μm and remaining metal filler as Cu for the entire simulation purpose. Our result confirms significant improvement in noise coupling using liners made...
With in the process temperature limit of less than 400 °C for via last technology, a simple method to improve the barrier ability of Ti layer in through Si via (TSV) has been studied. After annealing the TSV structures in vacuum at temperatures up to 400 °C, we did observe a tremendous improvement in leak current characteristics for SiO2 dielectric. It was found that the self-formed TiSix at the interface...
Complicated processes of through-silicon-via fabrication makes low yield of through-silicon-via mass production. Through-silicon-via redundancy is one of various ways that have been put forward to improve reliability of electrical interconnections. Allocation of through-silicon-vias is changed as redundant through-silicon-vias are added. Consequently, thermal dissipation and thermal mechanical reliability...
With the rapid increment of the power density and decrement of chip size, thermal management has become a critical problem in three-dimensional integrated circuit (3D IC). Through-silicon-via (TSV) is widely used to alleviate thermal problems thanks to its high thermal conductivity. However, thermal effectiveness of TSV in the thermal management varies in different situations. In this paper, based...
Foundry customers and makers of leading-edge devices are evaluating through-silicon via (TSV) for next-generation three-dimensional (3D) packaging. Scaling the diameter of the TSV is a major driver for improving system performance and cost. With smaller TSV diameters, back-to-front overlay becomes a critical parameter because via landing pads on the first metal level must be large enough to include...
Silicon interposer technology enables the integration of multiple silicon dies on it providing fine pitch interconnects for die-to-die communication and Through-Silicon Vias (TSVs) for package/PCB level connections. Therefore, this technology has been identified as a viable solution for logic and memory types of applications where higher bandwidth in required. In the paper, we characterize thick (t=3μm;...
This paper presents one fabrication process of a triple-layer stacked TSV interposer for switch matrix consisting of eight RF chips. There are about 600 TSVs in the interposer and the diameter of TSV is 40um with the aspect ratio being 4:1. The whole area of the interposer is 13.5 mm × 7.5mm and the thickness of the triple-layer stacked interposer is only about 0.7mm. After the process, the electrical...
In this paper, a differential vertical transition with through silicon vias (TSVs) in photonic integrated circuit die is presented. The vertical transition composes of TSVs providing connectivity between the die front side and back side, BEOLs and micro-bumps. No back side redistribution layer is required to keep the fabrication process simple with good electrical performance. The high frequency characteristic...
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