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This paper presents an experimental analysis of the impact of AC- and DC-type Negative Bias Temperature Instability (NBTI) stresses on the CMOS inverter DC response and robustness. The results reveal, on one side, that the inverter DC response under AC NBTI presents a parallel shift of that shown under DC NBTI. However, the AC- to DC-induced shift of the inverter logic threshold is found much less...
This paper presents an operational amplifier based on pseudo-CMOS blocks and integrated in a flexible a-IGZO TFT technology. The circuit consists of only nMOS transistors, and the pair of active loads is in a pseudo-CMOS configuration. These active loads allow various kinds of common mode feedback schemes or cross-coupled connection, typical for CMOS operational amplifiers. The proposed amplifier...
We have previously proposed a new digital CMOS circuit which combined subthreshold circuit and adiabatic logic circuit with ultra-low power consumption. Our proposed circuit which is driven by two AC power supply with different frequency and amplitude, and is adapted to be provided a margin of switching timing of input signal. In this paper, we show a skew tolerance analysis of subthreshold adiabatic...
A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode multiple-valued logic(MVL), is proposed. The dynamic ternary inverter, literal circuits, and quaternary inverter are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The...
In this paper we examine a digitally controllable Nauta structure implemented in a 65nm process and identify a strategy useful for calibrating the structure in such a way that a maximum gain is achieved. We propose an efficient and simple tuning procedure that could be the basis for an integrated on-chip calibration solution and investigate the feasibility of implementing it. The procedure would primarily...
This paper proposes a novel high frequency ring oscillator. The proposed ring oscillator consists of CMOS inverters which use simple capacitor based level shift circuits. The level shift circuit consists of only a capacitor and a MOSFET. Its power consumption is ideally zero. Thanks to the level shift circuits, transconductance and drain conductance of MOSFETs in CMOS inverters increase and high oscillation...
A new reconfigurable linearized low noise transconductance amplifier (LNTA) design for a software-defined radio receiver is presented. The transconductor design aims at realizing high linearity at RF in a way that is robust for Process, Voltage and Temperature variations. It exploits resistive degeneration in combination with a floating battery by-pass circuit and replica biasing to improve IIP3 in...
In this paper, the design of a single-chip RF Pulse-Width Modulator and Driver (PWMD) aimed at exciting a 80 W class-E GaN high-power stage at 435 MHz is described. For the required buffer size, avoiding potential ringing of the pulses within the buffer structure presents a major challenge in the design process. Therefore, a smaller chip capable of driving capacitive loads of up to 5 pF was initially...
We describe a silicon photonic optical modulator based on a MOS-capacitor and a low power 1V CMOS inverter-based driver IC. In an MZI configuration, this efficient modulator and driver IC combination can produce a 9dB extinction ratio at 28 Gbps, at a wavelength of 1310nm.
This paper deals with the design of a SAR-ADC with 8-bit resolution suited for bio-medical application. The design of the key components of the SAR ADC namely, DAC, Comparator and Sample and Hold circuit (S/H) has been carried out using current mode approach with the DAC operating at sub-threshold regime. The input current range is 10nA to 2.57μA with 10nA as the LSB. The circuit has been designed...
Technology scaling driven by the benefit of integration density, high-speed of operation and low-power dissipation, has overcome many barriers over the last four decades. Currently, it is facing even more hurdles, which are more critical than earlier. One of them is variability. Variability is becoming a metric of equal importance as power, delay, and area. This work attempts to perform power and...
Low power consumption has become a highly important concern for the designs. Glitches contribute to the dynamic power which itself is a major portion of the total power consumed by designs. A glitch is an undesired transition that occurs before intended value in digital circuits. A glitch occurs in CMOS circuits due to differential delay at the inputs of a gate. The paper describes a procedure to...
The locally implicit leapfrog scheme has been proposed as one of the signal/power integrity (SI/PI) circuit simulation techniques of an arbitrary shaped power distribution network (PDN) modeled by triangular meshes. This method can perform transient analysis several times faster than the explicit leapfrog scheme by employing a locally implicit scheme instead of the globally explicit leapfrog scheme...
The current paper aims to put forward the arrangement of a new high speed, low power synchronously clocked NOR-based JK flip-flop embracing modified Gate Diffusion Input (GDI) procedure in 45nm technology. The propounded design on comparison with a synchronously clocked NOR-based JK flip-flop employing the traditional CMOS transistors, transmission gates and Complementary Pass-Transistor Logic (CPL),...
This work details a process-portable test chip, fabricated in 65nm CMOS, specifically designed to measure radiation-induced soft error rate (SER) during operation at near-threshold. A variety of SRAM, register file (RF), and digital logic test structures are included that provide a comprehensive assessment of circuit sensitivities to radiation at low VDD. Neutron irradiation measurements of SRAM/RF...
Rigorous mathematical formulation of digital circuits, although accurate, consumes simulation time of a circuit designer who wishes to have a quick investigation of the effect of various device parameters on the electrical response of a circuit. This paper uses simple yet efficient method to calculate the average resistance of the transistors for finding the RC time constant and thereby the transient...
Dynamic circuits using n-channel multiple-input floating-gate MOS(FGMOS) transistors to realize binary and ternary logic are presented. In binary domino circuits, the n-channel FGMOS transistors are used to replace the nMOS logic block to simplify the circuit structure. By using the advantage that voltage signals are easy to be added by means of floating gate in multiple-input FGMOS transistor, a...
In this paper, four adiabatic types have been researches with TSMC 0.18μm library, where Vin=1.8V, frequency=1MHz. We have applied the adiabatic logic structure to further reduce the power dissipation of the PBCAM. In traditional CMOS, the power dissipation mainly occurs in the MOS transistor during input data switching, however, the adiabatic logic circuit takes an opposing direction to...
Spin Wave Devices (SWDs) are promising beyond-CMOS candidates. Unlike traditional charge-based technologies, SWDs use spin as information carrier that propagates in waves. In this scenario, the logic primitive for computation is the majority gate. The majority gate has a greater expressive power than standard NAND/NOR gates, allowing SWD circuits to be more compact than CMOS, already at the logic...
A digital-to-transcoductance converter is presented for use with digitally programmable Nauta structure operational amplifiers. The converter architecture consists of parallel connected tri-state CMOS inverters sized in such a way as to present a complete range of transconductance tunability at the expense of linearity and transconductance output range. Our converter architecture is analysed under...
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