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3D integration technologies using through-Si via (TSV) technologies are receiving increased interest. A wide diversity of technologies is being proposed and an increasing number of potential application areas are identified. Different application domains have different TSV requirements and justify different integration approaches. The most important challenges to a widespread use of 3D integration...
Impacts of electron trapping/detrapping on the negative bias temperature instability (NBTI) characteristics in silicon nanowire transistors (SNWTs) with metal gates are experimentally studied in this paper. It is demonstrated that large amounts of as-grown defects, including both electron traps and hole traps, are induced by nanowire structure due to multiple surface crystal orientations of the cylinder...
This paper describes a scalable reconfigurable computing system using a Silicon circuit board (SiCB) design approach. The design involves attachment of unpackaged FPGA and memory die to wafer scale silicon substrates. The resulting reconfigurable computing system has substantial density, cost, and power consumption and performance improvements relative to other known integration or construction methods...
A very simple electrochemical process is used to deposit platinum (Pt) and nickel (Ni) on silicon (Si) substrate to form Schottky junction. The electrical behaviors of these Schottky junctions are observed. We also used TCAD (SILVACO 3.2) to fabricate these Schottky junctions and to observe the electrical behavior of these devices, and it shows that experimental and simulated results are close.
GaN/AlGaN device technologies are reviewed aiming at the applications to power switching systems. SL (Super Lattice) capping and QA (Quaternary Alloy) over-layer techniques have been developed to reduce the on-resistance of GaN/ AlGaN HFET. Further, we achieved GaN on Silicon epitaxial growth technology with almost the same mobility keeping the same 2DEG density, which will make the cost comparable...
For sub-65 nm design, there can be many timing effects not explicitly and/or accurately modeled and simulated. For design-silicon timing convergence, this paper describes a novel path-based diagnosis approach that analyzes and ranks potential design related issues causing the unexpected timing effects. We explain in detail how a path can be encoded with a set of diverse "features" based...
Practical aspects of synthesis and applications of single-wall and multi-wall carbon nanotubes (SWNT and MWNT, respectively) are presented. Among numerous potential applications, utilization of nanotubes for interconnections in microelectronics and in gas sensors is considered in more detail. The issues related to compatibility of nanotubes synthesis and manipulation processes with the Si planar technology...
We have found that effective work functions of high-work function gate metals (p-metals) become small and Fermi level pinning of gate metals occurs after high temperature treatment as the same in the case in p+poly-Si gates. On the contrary, intrinsic hybridization between metal and high-k wave function at the interface is crucial factor to determine effective work function of gate metals after low...
We present recent studies on amorphous silicon (a-Si) based resistive switching nonvolatile memory devices. The devices exhibit excellent performance of high on/off resistance ratio, high yield, fast speed, long retention/endurance and are fully compatible with CMOS processing. High-density crossbar arrays were successfully demonstrated without degradation of the device performance as compared to...
Different wafer bonding techniques for heterogeneous integration are compared; in particular, the advantages and disadvantages of metal bonding using isothermal solidification (ITS) process are investigated. In applying the ITS metal bonding to Si and GaAs integrated circuits, two distinct approaches - pre-patterning and post-patterning, are developed and the resulting metal bond properties, such...
A thin palladium layer (~20 A) was selectively formed on top of amorphous germanium film before annealing and the effects of palladium layer on the lateral crystallization behavior of the amorphous germanium film were investigated through optical microscope, Raman spectroscopy, transmission electron microscopy, energy dispersion X-ray spectroscopy and selective area electron diffraction. Lateral crystallization...
Physical and electrical processes involved in the lifecycle failure of metal contacts in MEMS RF cantilever beam contact switches are of a great interest to switch designers. The main failure of MEMS contact switches occurs at the metal contacts. This paper describes a specially designed nanoindenter based experimental setup for characterizing the physics and mechanics of MEMS scale electrical contacts...
Silicene, a monolayer of silicon atoms packed into a two-dimensional honeycomb lattice is the challenging hypothetical reflection in the silicon realm of graphene, a one-atom thick graphite sheet, presently the hottest new material in condensed matter physics and nanotechnology. If existing, it would also reveal a cornucopia of new physics and potential applications. Here, we reveal the catalytic...
In this paper we present a promising method for the fabrication of MEMS accelerometers. The method should be easily adapted to fabricating other devices such as pressure sensors, gyroscopes, and micro mirrors as well. Of the device SOI wafer is used to fabricate the sensing element and glass wafer is used as the substrate to support the device and for metal interconnects and signal I/O. Wafer bonding...
Effect of the flat band voltage reduction (roll-off) in highly scaled high-k/metal gate stacks is discussed. The proposed mechanism explains the roll-off phenomenon as caused by the metal electrode/high-k dielectric-induced generation of positively charged oxygen vacancies in the interfacial SiO2 layer in the high-k dielectric stack. The model is consistent with the observed roll-off dependency on...
Carbon doped Si (Si:C) layer suppresses the boron diffusion and makes the steep channel profile; therefore, it is important to clarify the advantage of channel profile engineering using Si:C layer for the bulk planar nMOSFETs of post-32 nm technology node. In this paper, we demonstrate the merits of retrograde channel device with Si:C layer at 25 nm gate length, including the application for the bulk...
Silicon nanowire based discrete trapped charge-storage nonvolatile memory cell employing high-kappa dielectrics with metal gate is presented for the first time. The nanowire TAHOS (TaN/Al2O3/HfO2/SiO2/Si) memory fabricated using top-down method in nearly gate-all-around (GAA) architecture showed higher P/E speed than SONOS. In TAHOS, the erase speed is found almost equal to the program speed. The...
The process of hydrogen transportation into a silicon powder has been investigated. It is also established, that in the process of transition from nano- to microsizes is an accumulation of hydrogen takes place, both in volume, and on the surface of the powder.
This paper presents a fabrication technique that utilizes a combination of photolithography and mechanical lapping to achieve a micromachining process to overcome the limitations of conventional machining for realization of millimeter and submillimeter waveguide components. The fabrication process for the waveguide sections begins with spin cleaning a silicon wafer. The SU-8 micromachined part will...
We report on p-MOSFETs based on La2O3, Al2O3 and a mixture of both as high-k dielectric deposited by molecular beam epitaxy (MBE). Mobilities of about 140 cm2/Vs were achieved, which are 1.3 to 1.5 times larger than the universal hole mobility of Si/SiO2. This demonstrates the potential advantage of La2O3-based Ge p-MOSFETs over Si devices. The negative threshold voltages VT, which range between -0...
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