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We propose a novel 4-bit self-aligned SONOS-type nonvolatile memory (NVM) cell with a T-gate and I-shaped FinFET structure for practical implementation with high storage density and better reliability. In order to obtain enhanced reliability characteristics, a modified Fowler-Nordheim tunneling mechanism is employed for programming along the channel length direction, while a band-to-band hot hole...
A novel gate-all-around low-temperature poly-Si (LTPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced...
Potential well engineering is proposed for NAND Flash memory. With a variable (~2nm-4.3nm) tunnel barrier, the engineered well (EW) enhances tunneling of carriers during program/erase (P/E) to result in fast P/E, while it suppresses charge loss under the retention mode to result in good data retention. The EW also improves endurance, as it is insensitive to the P/E stress induced tunnel barrier degradation...
Reliability of charge trapping (CT) devices has been examined in detail, and the path to sub-30nm NAND flash is investigated. All CT devices are vulnerable to edge effects (non-uniform injection and non-uniform Vt along the device width). This degrades both the endurance and the ISPP programming efficiency, but the effect can be minimized by careful engineering. Metal gate and high-K dielectric can...
Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a 1Mb test chip was fabricated...
In this work we present an investigation on the program, retention and erase mechanisms of cylindrical gate-all-around charge-trapping memories. The numerical model accounts for tunnel injection of electrons and holes from the channel and the gate into the silicon nitride layer; for carrier transport, capture and emission in the nitride, and allows for both planar and cylindrical geometries. Simulations...
Erase characteristics of a SONOS-based structure are emulated not only for n+-poly and p+-poly gates but also for TaN-gate+Al2O3 combination. By incorporating our previous studies, performances including program, erase, and read disturb can be reviewed for both SONOS and TANOS devices. Unsurprisingly, it is hard to satisfy all requirements by using a SONOS device. In a TANOS device, an optimal bottom...
This publication investigates the program simulation of charge trapping memory devices in detail. Three different aspects of the simulation are highlighted which have a major impact on the program characteristics in trap based memories. The analysis is done by a comparison between measurement and simulation. It is shown that the trap capture cross section, the bottom oxide to storage nitride energy...
This paper carefully analyzes various charge-trapping NAND Flash devices including SONOS, MANOS, BE-SONOS, BE-MANOS, and BE-MAONOS. The erase mechanisms using electron de-trapping or hole injection, and the role of the high-k top dielectric (Al2O3) are critically examined. In addition to the intrinsic charge-trapping properties, the STI edge geometry in the NAND array also plays a crucial role in...
An improved model for charge injection through ONO gate stacks, that comprises carrier transport in the conduction band of the silicon nitride (Si3N4), is used to investigate the program/retention sequence of Si3N4 based (SONOS/TANOS) non volatile memories without making assumptions on the initial distribution of the trapped charge at the beginning of retention. We show that carrier transport in the...
In this paper, the authors developed the P/E model of NAND-type nitride-based charge trapping flash memories with transient ONO field, tunneling currents, trapped charge density and threshold voltage shift. The simulated results show acceptable V?? shift operation of SONOS NAND flash memory using FN and direct tunneling in P/E process. This modeling works account for the V?? shift as a function of...
We show that nearly 90 electrons can be stored at 30 nm dimensions of memory nodes, sufficient for reproducibility with having multi-bit memory windows, and that a minimum of tunneling oxide thickness is required to assure reliable retention characteristics. This work has achieved ultra-low number of electron storage while achieving high threshold shifts and demonstrates predictability through self-consistent...
Gate-all-around (GAA) MOSFET with single silicon nanowire is fabricated and applied to SONOS memory as a cell transistor for NAND flash string. Driving current over 1 uA, which is sufficient to NAND string, is obtained with single nanowire of ~7 nm width. Using FN tunneling conditions, VTH window of 4.5 V and fast program/erase (P/E) speed of ~10 us are obtained, respectively. The smaller nanowire...
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