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Ge/Si core/shell gate-all-round nanowire pMOSFET integrated with HfO2/TaN gate stack is demonstrated using fully CMOS compatible process. Devices with 100 nm gate length achieved high ION of ~946 ??A/??m at VG - VT = -0.7 V and VDS = -1 V and on/off ratio of 104 with decent subthreshold behavior. Significant improvement in hole mobility and ballistic efficiency is demonstrated as a result of core/shell...
A new generation of Power MOSFET technology has been introduced. The devices are manufactured in a standard 0.35??m CMOS production line with only few process modules being adapted for the requirements of vertical power transistors with a 2x improvement in Figure of Merit (FOM). This improvement results mainly from the reduction in Miller capacitance.
Distributed effects may appear in active devices in mm-wave CMOS integrated design. In this paper we have analyzed the distributed effects in the intrinsic MOS transistor. Non-quasi static effect has been reviewed and its importance in mm-wave band has been demonstrated by simulations in the foundry design kit for STMicroelectronics 90nm CMOS technology. The distributed effect of MOS transistor has...
A CMOS low-dropout regulator (LDO) with high power supply rejection (PSR) characteristics is presented in this paper. By utilizing an optimized error amplifier, which feedforward the supply ripples into the gate of power transistor so as to maintain a constant gate-source voltage in power transistor under supply ripples, the proposed LDO provides high PSR capability. A prototype of the LDO has been...
Fully integrated MESFETs have been shown to work on multiple commercial silicon-on-insulator (SOI) and silicon-on-sapphire (SOS) CMOS processes without changing a step in the process flow. The unique features of the MESFET including depletion mode operation, breakdown voltages in excess of 50 V, and easy to adjust, but well controlled threshold voltages have given the designers a cost-free way to...
This paper presents two novel Floating Current Source (FCS) based CMOS negative second generation current conveyor (CCII-) realizations suitable for very large scale implementation. The proposed realizations provide high voltage and current tracking accuracy, as well as large voltage and current transfer bandwidths. Simulations show that the first proposed wide band CCII- bandwidth is about 972 MHz...
This paper illustrates the rail-to-rail capability of a single-pair bulk-driven CMOS input stage operated from an extremely low supply voltage. A composite input stage is also introduced for performance comparison, based on experimental data obtained in standard 0.35 mum CMOS technology with a supply voltage of 1 V. Measurements demonstrate the rail-to-rail suitability of the single-pair input stage...
A novel class AB second-generation CMOS current conveyor (CCII) is presented. Class AB operation is achieved without increasing supply voltage requirements or power consumption. The circuit also features very low input resistance at terminal X. The CCII has been fabricated in a 0.5-mum CMOS technology. Measurement results using a dual supply voltage of plusmn1.65 V show a THD of -60 dB at 120 kHz...
A new method for improving the frequency response of an all transistor simulated CMOS inductor bandpass filter is proposed. It is shown that a significant increase of the central frequency up to 800 MHz or even more can be obtained by introducing a supplementary resistor connected to the gate of one transistor. The method makes also use of negative resistances to compensate the inductor losses. Small...
The feasibility of using standard 0.18 mum CMOS technology for low cost wideband monolithic microwave integrated circuits (MMICs) at ~20 GHz is demonstrated. Two monolithically integrated distributed oscillators with n-FET gain cells are designed having four and three stages respectively, Coplanar waveguides used as the on-chip inductive elements. MOS Varactors are employed to tune the frequency,...
This paper presents an integrated digital class D audio power amplifier output stage implemented in a 40 V, 0.35 mum HV-CMOS technology. The integrated output stage consists of a full H-bridge, gate drivers, bootstrap diodes and protection circuits. Its performance was found to be better than previously published output stages implemented in SOI based BCD processes, which are typically more complex...
Device scaling is critical for continuing trend of more functionality in a chip. Traditional planar CMOS scaling is increasingly difficult due to limitations in processing and material properties, device structure and reliability. In this paper we will summarize recent advances in these areas, which will enable technology scaling as per Moore's law.
The substrate resistance of 45 nm CMOS devices shows a strong dependence on the distance between the device edge and the substrate ring; as well as on the number of sides that the device is surrounded by the contact ring. We find that the unilateral gain is impacted by the substrate resistance (Rsx) through the gate-body capacitance feedback path at low to medium frequencies (< 20 GHz). At mm wave...
This paper presents the design and analysis of a 3-5 GHz ultra-wideband (UWB) low-noise amplifier (LNA) in a 0.18 mum CMOS process. The proposed LNA consists of two stacked common-source stages which enable sufficient gain and wide operating bandwidth. Simulation results show a power gain of 14 dB with a variation less than 0.5 dB over 3-5 GHz, input and output return loss lower than -9 dB and -8...
Sigma-Delta modulator ADCs used in signal processing applications are usually implemented by switched-capacitor (SC) circuits and CMOS transmission gates. Clock feed-through effect is one of the main non-ideal parameters existing in SC integrators degrading modulator total SNDR and its linearity. In this paper, a comprehensive analysis of clock feed-through effect on CMOS transmission gates on both...
A method to approximate nFET passgate resistance using the compact EKV model is presented. The model picks a mobility that has a greater effect on channel current than higher-order MOS effects in order to approximate the worst-case current over a drain-source voltage range. The model is compared to data taken from an IC that was fabricated in a 0.5 mum, scalable CMOS process available through MOSIS.
This paper investigates the viability of using leakage power consumption as a source of side channel information. The side channel effect is characterized in leakage power. It is shown that the increasing trend of leakage power is highly correlated with security vulnerability of cryptosystems. Addressing the severity of the side channel threat in nanoscale Cryptosystem-on-Chip (CoC), we examine the...
We report the first demonstration of a surface channel inversion-type In0.53Ga0.47As n-MOSFET featuring gold-free palladium-germanium (PdGe) ohmic contacts and self-aligned S/D formed by silicon and phosphorus co-implantation. A gate stack comprising TaN/HfAlO/In0.53Ga0.47As is also featured. Excellent transistor output characteristics with high drain current on/off ratio of 104, high peak electron...
In this paper, we have systematically investigated the factors for performance enhancement on sub-32nm CMOS technology. We report that PMOS gains the drive current by slim spacer, S/D silicide resistance reduction by e-SiGe, and compressive CESL. The three factors improve the PMOS performance by 7%, 10% and 25% respectively. Combined with the three factors can gain the device drive current 30%. In...
In this paper, we study the impact of gate oxide short (GOS) defects in SRAM core-cells in terms of stability in static condition. Existing studies have applied split GOS models that require the use of non-realistic oversized designs. The novelty of this research is the application of a non-split GOS model, which allows the study of the electric deviation of the behavior of realistic minimal sized...
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