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It is believed that new technologies tend to initiate with new materials and manufacturing processes, which are used for new products. Magnetoelectric multiferroics are the class of materials which have coexistence of magnetic and ferroelectric properties, with coupling between two order parameters. These materials therefore find novel applications in multiple memories apart from MEMS sensors and...
Gate misalignment and process variations are important challenges in sub-20 nm gate length planar double-gate (DG) MOSFET devices. For the first time, we demonstrate a misalignment- and process variations-aware device optimization strategy for a DG-MOSFET. Using underlaps and high-kappa offset-spacers, we show that the robustness of the device to gate misalignment and process variations can be improved...
Ultra thin (~6-7 nm) silicon-oxynitride films have been deposited on Strained-Si/Si0.8Ge0.2 layers at high temperature of 900degC and 1000degC using rapid thermal nitridation in O2+N2 ambient. The border trap (Qbt) generation using the hysteresis in high-frequency capacitance-voltage (C-V) characteristics under both constant current stressing (CCS) and constant voltage stressing (CVS) has been analyzed...
The interface trap density of fresh TiN/TaN gated HfO2/SiO2/Si/epi-Ge pMOSFETs is measured using the DCIV technique. Its temperature dependence is also discussed here. We observe a polarity dependent DCIV peak shift. The bias temperature stress induced interface trapped charge and oxide trapped charge shifts are also systematically investigated in this work.
The paper presents implementation of several surface micromachined tunneling accelerometer structures. This work also records the study of their relative performance in order to achieve high sensitivity and high dynamic range for mu-g measurement with low cross axis sensitivity.
This paper presents a physics-based compact dc model for high voltage silicon on insulator lateral double diffused MOS (SOI-LDMOS) transistor, assuming uniform doping for the channel. It uses MM20 model for the channel and drift region under the thin gate oxide, and proposes a new model for the drift region under the field oxide. This model shows that the current at higher gate voltages in SOI-LDMOS,...
Results of small-signal modeling of 0.5 um gate length pseudomorphic HEMTs are presented here. Modeling included scalability with respect to number of gate fingers, gate width and gate bias dependence of Equivalent Circuit Parameters (E.C.Ps). p-HEMTs with gate widths of 100 mum and 150 mum, each with varying number of gate fingers (2, 4, 6) keeping all other structural parameters constant were fabricated...
This work establishes a novel circuit simulation methodology for organic thin film transistors (OTFTs). Because of a lack of well developed physical models for OTFTs and due to the limitations of conventional parameter extraction techniques, the approaches presented in this work come in handy for circuit designers. The first approach uses a look-up table (LUT) model, which is implemented in a general...
This paper, presents an analytical modeling of electron density in the active silicon region, the effect of back gate bias on front gate threshold voltage and estimation of the subthreshold slop for Double Gate MOSFETs. The various analyses have been carried out for symmetric and asymmetric structures where the asymmetric nature has been considered by virtue of altering the back gate insulator thicknesses...
The full complex band structure model in ultra-scaled (~10 nm) DG MOSFETs is studied. Building on a previous 2D / 1D model, we have included a more realistic band structure to describe the quantum transport. The empirical tight-binding Hamiltonian, rather than that based on effective mass theory, is used directly in the NEGF formalism. The nearest and second nearest neighbor coupling are taken into...
LSMO/ZnO p-n hetero-junctions have been fabricated by pulsed laser deposition on p-Si (100) substrates. Grazing incidence XRD, FESEM, AFM, electrical I-V and photoluminescence study have been carried out to investigate the structural, film thickness, topographical, rectifying, photo-response and photoluminescence properties of the structures. The LSMO/ZnO junction, exhibits rectifying behavior for...
In this paper, we derive an analytical model of drain current for an Undoped 4-T asymmetric double gate MOSFET based on the solution of the 1D Poisson's equation. The equations are valid for both the subthreshold and superthreshold regime of operation. The current is formulated using the Pao-Sah's double integral method. The model can be used to study the effect of the different gate voltages, gate...
Recently, the industry has focused a great deal on the use of non-planar multi-gate device structures. Many drain current models are available for undoped thin silicon channel double-gate (DG) silicon-on-insulator (SOI) MOSFET, but these models do not take charge coupling effect into account leading to an error of more than 20 percent for silicon channel thicknesses below 30 nm. Hence, we present...
In this paper we report for the first time, a method of generating wide gate recess structure in single recess step by the help of a bi-layer lithography technique, which can be used to generate varying gate recess width by varying developmental time. It is established that the gate recess structure decides the Schottky breakdown voltages in these devices. The distance from gate edge-to-n+ in the...
We modify the macroscopic equations proposed by Valet and Fert for current perpendicular to the plane of a magnetic bilayer. Considering different spin bands for the spin-up and spin-down electrons, we calculate the charge accumulation near the interface along with the spin accumulation. This gives rise to a voltage drop at the interface, and causes the resistance to depend on the relative degree...
GaAs MESFET-based switches suffer from high insertion losses. As an alternative, GaAs RF MEMS have shown great promise due to high isolation, low insertion losses, and wide bandwidths. Some factors constraining the fabrication have been suitable planarization techniques, quality of metallisation, stress in the beams, and elimination of stiction of beams to the central signal electrode. Quality of...
A framework for modeling of quantum mechanical effects in the ultra-thin body Nanoscale double-gate (DG) FinFET is presented. For subthreshold conditions, we have assumed that the electrostatics is dominated by capacitive coupling between the body electrodes, thus the potential is obtained as a solution of the 2D Laplace equation with the help of conformal mapping techniques. In the near-threshold...
An experimental investigation on oxide positive charge buildup in sub 3-nm silicon dioxide (SiO2) films is presented during direct tunneling (DT) of electrons at -1.8 V of gate bias. The measurement results can be best explained by hole generation via anode hole injection (AHI) mechanism and the subsequent trapping of holes in the as-fabricated neutral hole traps in the oxide. A comparative study...
Three different noise models are investigated from physical perspective using hydro-dynamic device simulation of 1D SiGe-HBT. An intuitive noise model formulation is proposed based on the 1st and 2nd order charge partitioning across base-emitter and base-collector regions. It is verified that proposed model improves the modeling of base current noise and correlation between the base and collector...
A two step gate dielectric deposition technique on GaN, viz. thermal oxidation of Low Pressure Chemical Vapor Deposited (LPCVD) silicon is reported. Current-Voltage (I-V) and Capacitance-Voltage (C-V) characterization of the Metal Insulator Semiconductor (MIS) capacitors are carried out to assess the interface properties. MIS devices with thermal oxide show improved I-V characteristics compared to...
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