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In this paper, we have systematically investigated the factors for performance enhancement on sub-32nm CMOS technology. We report that PMOS gains the drive current by slim spacer, S/D silicide resistance reduction by e-SiGe, and compressive CESL. The three factors improve the PMOS performance by 7%, 10% and 25% respectively. Combined with the three factors can gain the device drive current 30%. In...
In this paper, we have systematically investigated the impact of the thermal-induced stress relaxation on biaxially strained silicon-on-insulator (SSOI) CMOS. We found that STI anneal would degrade nMOS drive current by 12% but improve pMOS by 17% in long channel SSOI devices. However, skipping LDD anneal would increase extension resistance and cause performance degradation. In addition, it is found...
An advanced partially-depleted (PD) silicon-on-insulator (SOI) CMOS device was optimized with full consideration of the floating body effect (FBE) using channel and S/D engineering. By adjusting channel and S/D implants' species and dosage, the S/D doping profiles across transistor sidewall junction will be shown to reduce floating body effects and sidewall junction capacitance. Reduced sidewall junction...
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