Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
A CAM-based (Content Addressable Memory) system for fast Watermarking extraction has been proposed and implemented on hardware system using FPGA device. The system has a simple structure, does not employ any Central Processor Units (CPUs) or complicated algorithms for extracting hidden information. The authors take advantages of CAM which has an ability of parallel multi-match mode for designing the...
This paper presents a FPGA (Field Programmable Gate Array) based secured speech signal communication system. The system consists of compression, encryption and water- marking. Watermark provides authentication and ownership verification. Encryption is used for security of watermark and voice signal. As random numbers are used as a key for the encryption process, the signal is secured for both wired...
Two elliptic curve scalar multiplications (ECMLT) are used in some important elliptic curve encryption algorithms, a pseudo-pipelined VLSI architecture of two ECMLTs over GF(2m) is proposed for these algorithms. The proposed architecture includes three word-serial finite field (FF) multipliers, and each FF multiplier has word size w. Implemented using FPGA, two ECMLTs are computed in approximately...
This paper presents a method for generating chaotic pseudo random (PR) sequence, which uses a novel three-dimensional (3-D) chaotic system and can generate both digital chaotic PN sequences and continuous time chaotic noise signals. This technique is derived from the idea of combining DSP builder tool with Matlab/Simulink and Quartus II software and is based on the direct discreteness and quantization...
Protecting an implementation against side channel analysis for reverse engineering (SCARE) attacks is a great challenge and we address this challenge by presenting a first proof of concept. White-box cryptography has been developed to protect programs against an adversary who has full access to their software implementation. It has also been suggested as a countermeasure against side channel attacks...
This article mainly describes a way of designing an efficient pseudo-random number generator. Combining that the cellular automaton has many characteristics, such as simple rules of the component units, the local connectivity of units, the high degree of parallelism in information processing, and the complicated global characteristics, we use the rule 30 of one-dimensional cellular automaton to drive...
The advanced encryption standard, AES, is commonly used to provide several security services such as data confidentiality or authentication in embedded systems. However designing efficient hardware architectures with small hardware resource usage and short critical path delay is a challenge. In this paper, a new technique for the FPGA implementation of the MixColumns transformation, an important part...
Research on Differential Power Analysis (DPA) is becoming more and more popular nowadays. Against different hardware, DPA attack will lead to different results, e.g. attack on FPGA is easy but on ASIC is relatively difficult. However, how could we draw the conclusion that we finish a successful attack? How to build the connection between result data and successful rate is a meaningful topic. Same...
A high assurance multiplexer can be used to combine all channels of a MSLS system into a single stream that accommodates all of the channels to be transported at each end of the multiplexed link. The multiplexer/demultiplexer is termed ??high assurance?? because it guarantees the integrity of the channel separation process such that, even under multiple failure conditions, the design assures that...
Facing the rapid development of multimedia and Internet technology, the demand of information on the real-time communications and confidentiality is increasing highly. The system, mainly based on a chaotic encryption algorithm and combined with multi-level shuffle exchange network, is designed and implemented a high-speed data encryption system. After settling the problem of conflict of access caused...
In Embedded Systems, the calculation of RSA cryptographic operations is sometimes hard to achieve if time constraints must be observed. In the following, we present an approach to increase processing power regarding cryptographic operations using FPGA (Field Programmable Gate Array) technology. The FPGA, which is present in many designs anyway, computes parts of the operations, allowing the embedded...
A silicon physical unclonable function (PUF), which is a die-unique challenge-response function, is an emerging hardware primitive for secure applications. It exploits manufacturing process variations in a die to generate unique signatures out of a chip. This enables chip authentication and cryptographic key generation. A ring oscillator (RO) based PUF is a promising solution for FPGA platforms. However,...
In this article, we show how the use of a bio-inspired dynamic task replication algorithm, in the context of stream processing, can be used to significantly improve the performance of embedded programs. We also show that this programming methodology, which is not tied to a particular implementation, can also be used as an heuristic for task mapping in the context of embedded multiprocessors systems...
This paper proposes a method for measuring hardware configurations for trusted platforms based on field programmable gate arrays (FPGA). The proposed system setup allows for partial reconfiguration as well as full reconfiguration of FPGA devices that can be used additionally as trusted platforms. In the system, slots are defined for fast partial dynamic reconfiguration. Predefined IP blocks may be...
Simple power analysis attacks with chosen-message techniques were applied to an RSA processor implemented with standard CMOS technology on ASIC, and the different characteristics of power waveforms caused by two types of implementation (ASIC and FPGA) were investigated in detail. We also applied comparative power analysis an advanced power analysis attack in which a pair of input data was used to...
This paper presents a new method for creating TRNGs in Xilinx FPGAs. Due to its simplicity and ease of implementation, the design constitutes a valuable alternative to existing methods for creating single-chip TRNGs. Its main advantages are the high throughput, the portability and the low amount of resources it occupies inside the chip. Therefore, it could further extend the use of FPGA chips in cryptography...
The main contribution of this paper is to present efficient hardware algorithms for the modulo exponentiation PE mod M used in RSA encryption and decryption, and implement them on the FPGA. The key ideas to accelerate the modulo exponentiation are to use the Montgomery modulo multiplication on the redundant radix-64 K number system in the FPGA, and to use embedded 18 times 18-bit multipliers and embedded...
The security of audio data in high end communication applications like satellites and radars is an issue of concern these days. Designing a processor at the chip level for this requirement is by itself a challenge to VLSI engineers. This paper aims to design a HDL based novel audio subword sorter unit, which is less complex in structure and highly efficient in terms of security. In this paper, we...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.