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Two unique gate oxide failure mechanisms are associated with deep trench processes for a 0.18 μm power semiconductor device. One failure mode is a “mini-LOCOS” defect, that is due to inadvertent oxidation of Si in the active area during deep trench oxidation. The other failure mode is due to slip associated with dislocations from the deep trenches. These defects are eliminated by optimizing the SiN...
Researchers have conducted extensive research on the fatigue mechanism of silicon microstructures. But the key step in some mechanisms that localized oxide can thicken at high stress concentration sites after fatigue failure lacks support. Based on the Deal-Grove model of the thermal oxidation of silicon, we have proposed a chemical kinetics principle of cyclic stress enhanced oxidation: Tension can...
This paper suggests an improved method to round off the concave corners of the deep trenches formed by plasma etch. The corner rounding technique, sacrificial oxidation (SACOX) before gate oxidation, has been practiced on the shallow trench isolation (STI) to improve the CMOS leakage performance. However, the direct implementation of the SACOX on the deep trenched MOSFET having less than 0.5 um trench...
Wafer level reliability (WLR) issues of DRAM cell and peripheral transistors are discussed. Since the 70 nm technology node, recessed transistors have been accepted for assuring data retention time of DRAM cell transistors. Various recessed transistor structures suggest that the most important issue in reliability, in addition to optimizing data retention time, is the elimination of local regions...
For the first time, a metal-insulator-semiconductor (MIS) device that consists of silicon (Si) nanocrystals embedded in a silicon oxide film is proposed to investigate how the charge accumulation and relaxation can be manipulated by the nanocrystals for high reliable capacitive RF MEMS switch. A tri-layer structure, used as the insulator in our MIS device, comprises a thicker (about 100 nm) rapid...
In this paper, the material and electrical properties of newly developed gate dielectrics were investigated by SIMS depth profile. NMOS transistor structures were fabricated by thermally grown radical oxidation (TGRO) in a batch type thermal processor and densified by plasma re-oxidation in a slot processor, followed by post oxidation anneal process to cure the plasma damage and nitridation in N2...
We have observed new charge trapping phenomena in sub-80-nm DRAM recessed- channel-array-transistor (RCAT) after Fowler-Nordheim (FN) stress. Gate stack process strongly affected the charge trapping and the trap generating in oxide bulk and interface of RCAT. According to the trapped charges and/or the generated traps after FN stress, the data retention time and writing capabilities of DRAM were dramatically...
This paper presents quantitative 2D stress dependent simulations of the Sealed Interface Local Oxidation (SILO) structure. In the SILO structure, the oxidation mask consists in a NitrideI/Oxide/Nitride II stack, in which the thin Nitride I layer is directly sealed on the silicon surface. A very thin oxide layer is considered between the silicon and the nitride-I layer in which the oxidant diffusivity...
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